2008 45th ACM/IEEE Design Automation Conference最新文献_第5页

FPGA area reduction by multi-output function based sequential resynthesis 基于顺序重合成的多输出函数的FPGA面积缩减

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391478

Yu Hu, Victor Shih, R. Majumdar, Lei He

引用次数: 16

Automatic synthesis of clock gating logic with controlled netlist perturbation 控制网表扰动的时钟门控逻辑自动合成

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391637

A. Hurst

引用次数: 31

A generalized network flow based algorithm for power-aware FPGA memory mapping 基于广义网络流的功耗感知FPGA内存映射算法

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391479

Tien-Yuan Hsu, Ting-Chi Wang

引用次数: 1

Predictive dynamic thermal management for multicore systems 多核系统的预测动态热管理

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391658

Inchoon Yeo, C. Liu, Eun Jung Kim

{"title":"Predictive dynamic thermal management for multicore systems","authors":"Inchoon Yeo, C. Liu, Eun Jung Kim","doi":"10.1145/1391469.1391658","DOIUrl":"https://doi.org/10.1145/1391469.1391658","url":null,"abstract":"Recently, processor power density has been increasing at an alarming rate resulting in high on-chip temperature. Higher temperature increases current leakage and causes poor reliability. In this paper, we propose a Predictive Dynamic Thermal Management (PDTM) based on Application-based Thermal Model (ABTM) and Core-based Thermal Model (CBTM) in the multicore systems. ABTM predicts future temperature based on the application specific thermal behavior, while CBTM estimates core temperature pattern by steady state temperature and workload. The accuracy of our prediction model is 1.6% error in average compared to the model in HybDTM, which has at most 5% error. Based on predicted temperature from ABTM and CBTM, the proposed PDTM can maintain the system temperature below a desired level by moving the running application from the possible overheated core to the future coolest core (migration) and reducing the processor resources (priority scheduling) within multicore systems. PDTM enables the exploration of the tradeoff between throughput and fairness in temperature-constrained multicore systems. We implement PDTM on Intel's Quad-Core system with a specific device driver to access Digital Thermal Sensor (DTS). Compared against Linux standard scheduler, PDTM can decrease average temperature about 10%, and peak temperature by 5degC with negligible impact of performance under 1%, while running single SPEC2006 benchmark. Moreover, our PDTM outperforms HRTM in reducing average temperature by about 7% and peak temperature by about 3degC with performance overhead by 0.15% when running single benchmark.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125758947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 205

(Bio)-Behavioral CAD (生物)行为CAD

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391562

M. Potkonjak, F. Koushanfar

引用次数: 1

WavePipe: Parallel transient simulation of analog and digital circuits on multi-core shared-memory machines WavePipe:多核共享内存机器上模拟和数字电路的并行瞬态仿真

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391531

Wei Dong, Peng Li, Xiaoji Ye

{"title":"WavePipe: Parallel transient simulation of analog and digital circuits on multi-core shared-memory machines","authors":"Wei Dong, Peng Li, Xiaoji Ye","doi":"10.1145/1391469.1391531","DOIUrl":"https://doi.org/10.1145/1391469.1391531","url":null,"abstract":"While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarsegrained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardying convergence and accuracy. As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130051603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Challenges in using system-level models for RTL verification 使用系统级模型进行RTL验证的挑战

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391676

Kelvin Ng

引用次数: 2

Formal datapath representation and manipulation for implementing DSP transforms 实现DSP转换的形式化数据路径表示和操作

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391572

Peter Milder, F. Franchetti, J. Hoe, Markus Püschel

引用次数: 54

DeMOR: Decentralized model order reduction of linear networks with massive ports 具有大量端口的线性网络的分散模型降阶

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391577

Boyuan Yan, Lingfei Zhou, S. Tan, Jie Chen, B. McGaughy

{"title":"DeMOR: Decentralized model order reduction of linear networks with massive ports","authors":"Boyuan Yan, Lingfei Zhou, S. Tan, Jie Chen, B. McGaughy","doi":"10.1145/1391469.1391577","DOIUrl":"https://doi.org/10.1145/1391469.1391577","url":null,"abstract":"Model order reduction is an efficient technique to reduce the system complexity while producing a good approximation of the input-output behavior. However, the efficiency of reduction degrades as the number of ports increases, which remains a long-standing problem. The reason for the degradation is that existing approaches are based on a centralized framework, where each input-output pair is implicitly assumed to be equally interacted and the matrix-valued transfer function has to be assumed to be fully populated. In this paper, a decentralized model order reduction scheme is proposed, where a multi-input multi-output (MIMO) system is decoupled into a number of subsystems and each subsystem corresponds to one output and several dominant inputs. The decoupling process is based on the relative gain array (RGA), which measures the degree of interaction of each input-output pair. Our experimental results on a number of interconnect circuits show that most of the input- output interactions are usually insignificant, which can lead to extremely compact models even for systems with massive ports. The reduction scheme is very amenable for parallel computing as each decoupled subsystem can be reduced independently.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127829205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement 提高良率的自旋转矩传递磁随机存储器(STT MRAM)阵列失效概率建模与统计设计

2008 45th ACM/IEEE Design Automation Conference Pub Date : 2008-06-08 DOI: 10.1145/1391469.1391540

Jing Li, C. Augustine, S. Salahuddin, K. Roy

引用次数: 88