Challenges in using system-level models for RTL verification

Abstract

In modern day digital design flow, high-level models written in C and C++ serve multiple purposes, one of which is to aid verification of register-transfer level (RTL) hardware models. These high-level models, also called system-level models (SLMs), act as reference models for hardware designs created at the RTL level. They define the correct behavior for the RTL hardware design under verification. Written in a programming language (or similar) and therefore executable, they are used extensively in both simulation-based verification and formal equivalence checking. This paper presents how SLMs fit into the different RTL verification schemes and the challenges involved in the various verification flows. Input stimulus generation based on formal verification technology is introduced as a new way to improve simulation coverage. This paper also covers other techniques engineers use to meet various challenges encountered in RTL verification.