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Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)最新文献

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Mixed 2-4 state simulation with VCS 使用VCS进行混合2-4状态模拟
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588537
H. K. Chaudhry, P. Eichenberger, D. R. Chowdhury
{"title":"Mixed 2-4 state simulation with VCS","authors":"H. K. Chaudhry, P. Eichenberger, D. R. Chowdhury","doi":"10.1109/IVC.1997.588537","DOIUrl":"https://doi.org/10.1109/IVC.1997.588537","url":null,"abstract":"To meet the demand for higher performance, today's logic simulators are supporting 2 state simulation. Within Chronologic Simulation's VCS simulation system, we have implemented an elaborate infrastructure to support mixed 2-4 state simulation in Verilog. The paper presents our approach to allow mixed 2-4 state simulation while retaining compliance to Verilog HDL language and its simulation semantics. The key issues that need consideration for mixed 2-4 state simulation are discussed in detail. The results obtained by running VCS regression test suite and OVI regression test suite are summarized.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"433 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115602257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Pre- and postsynthesis simulation mismatches 合成前和合成后模拟不匹配
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588528
H. Howe
{"title":"Pre- and postsynthesis simulation mismatches","authors":"H. Howe","doi":"10.1109/IVC.1997.588528","DOIUrl":"https://doi.org/10.1109/IVC.1997.588528","url":null,"abstract":"With the widespread adoption of top-down design methodologies using HDL and synthesis, RTL models have become the \"golden\" design database. However, ASIC and FPGA vendors still require a gate level netlist as the official sign-off design. Model ambiguities in RTL designs can cause differences between RTL and synthesized netlist designs. These differences in the best case cause simulation mismatches between RTL and gate designs. In the worst case, if not detected in simulation they can result in faulty hardware. This paper covers common sources of ambiguity in RTL models. Solutions are provided for avoiding these situations. Some basic simulation debug tips are provided to help identify these errors in simulation with both VHDL and Verilog. These examples are based on Synergy (Cadence's synthesis tool) but also apply to synthesis in general.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125999524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Implementation of a PCI bus virtual driver using PLI, named pipes, and signals 使用PLI、命名管道和信号实现PCI总线虚拟驱动程序
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588526
D. Hahn, J. Russack
{"title":"Implementation of a PCI bus virtual driver using PLI, named pipes, and signals","authors":"D. Hahn, J. Russack","doi":"10.1109/IVC.1997.588526","DOIUrl":"https://doi.org/10.1109/IVC.1997.588526","url":null,"abstract":"In designing a complex ASIC it is often the case that adequate testing cannot be performed without modeling the high level environment where the ASIC will eventually reside. One approach for developing these models is to write a description of the environment in the native simulation language (Verilog or VHDL) that is being used to develop the ASIC. While designing a complex ATM network interface chip with a PCI bus interface it became necessary to develop a driver model to check correctness of operation. We decided to develop a co-design environment which would allow us to develop a real driver (in C++) which would interact with the current hardware model in RTL. This would benefit the project in two ways. First the driver writer would not need to learn a new language and could re-use code, and secondly, there would be a fully developed driver when the chip was ready to be tested. This approach, which uses UNIX named pipes and signals, allowed us to have driver software written before the chip had been manufactured and facilitated our regression methodology. This paper describes the architecture of the simulation interface.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114779744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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