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Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)最新文献

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High-level architectural simulation of the Torus Routing Chip 环形路由芯片的高级体系结构仿真
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588531
L. Natvig
{"title":"High-level architectural simulation of the Torus Routing Chip","authors":"L. Natvig","doi":"10.1109/IVC.1997.588531","DOIUrl":"https://doi.org/10.1109/IVC.1997.588531","url":null,"abstract":"This paper presents a simulation model of the Torus Routing Chip (TRC) written in Verilog. The model represents the functional behaviour of the routing chip down to the flit (byte) level. The TRCs are self-timed and interconnected in a 4 by 4 torus (mesh with wrap-around) having unidirectional channels along the x and y-dimension. To avoid deadlock situations, the TRC implements two virtual channels on every physical channel. The model is presented in a top down manner with emphasis on the modelling of the packet routing algorithm, asynchronous channels, controlled access to shared resources and the increased complexity caused by virtual channels. The testing of the model as well as experience from using Verilog to develop a high-level architectural simulation is discussed.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123612101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
OMI-a standard model interface for IP delivery omi -用于IP交付的标准模型接口
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588538
D. Dunlop, K. McKinley
{"title":"OMI-a standard model interface for IP delivery","authors":"D. Dunlop, K. McKinley","doi":"10.1109/IVC.1997.588538","DOIUrl":"https://doi.org/10.1109/IVC.1997.588538","url":null,"abstract":"The Open Model Forum (OMF) industry consortium has developed a simulator-independent and HDL-independent interface between an EDA tool such as a simulator and a \"black box\" model of a block of intellectual property. This interface, called the Open Model Interface (OMI), allows interoperable models to be developed, distributed and used with any compliant tool without exposing the internal structure or operation of the model. An IEEE effort was recently launched to begin the process of standardizing OMI. The need for OMI is motivated, expected usage scenarios are discussed, and an overview of the technical solution is presented.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"527 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Synthesis support for design partitioning 对设计分区的综合支持
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588529
J. Willoughby
{"title":"Synthesis support for design partitioning","authors":"J. Willoughby","doi":"10.1109/IVC.1997.588529","DOIUrl":"https://doi.org/10.1109/IVC.1997.588529","url":null,"abstract":"As designs become larger and larger it becomes necessary to partition the design, not only to meet synthesis tool restrictions, but also to perform parallel design processing by multiple engineers and/or on multiple machines. Partitioning requires the assignment of timing and loading budgets across module boundaries. This is an inefficient and time-consuming task if performed by hand. Logic synthesis tools can utilize techniques of constraint propagation combined with hierarchical controls to perform this task automatically. This approach will result in improved results and shorter design times.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127094391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A general purpose simulation environment for HDL based verification 基于HDL验证的通用仿真环境
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588527
S. Rajadnya, A. Palnitkar
{"title":"A general purpose simulation environment for HDL based verification","authors":"S. Rajadnya, A. Palnitkar","doi":"10.1109/IVC.1997.588527","DOIUrl":"https://doi.org/10.1109/IVC.1997.588527","url":null,"abstract":"With designs becoming increasingly complex, creating a simulation environment has become a very important part of the entire design cycle. The purpose of this paper is to describe a simulation environment which helps in reducing development time and making the simulation environment more flexible. We study a novel method for creating a simulation environment of a proprietary bus architecture (henceforth called PBA). After analyzing the PBA architecture, we decided to have 50,000 transactions in order to cover all the possible test scenarios. Our task was to create 50,000 transactions as a part of the PEA verification environment. We decided to create parametrized tests which can be reused. This method has helped us in reducing development time from six man months to approximately two man months.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analog design with Verilog-A 使用Verilog-A进行模拟设计
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588533
I. Miller, D. Fitzpatrick, R. Aisola
{"title":"Analog design with Verilog-A","authors":"I. Miller, D. Fitzpatrick, R. Aisola","doi":"10.1109/IVC.1997.588533","DOIUrl":"https://doi.org/10.1109/IVC.1997.588533","url":null,"abstract":"Verilog-A is a language to describe analog behavior. It is an extension to the IEEE 1364 Verilog Hardware Description Language (HDL) specification. A complete definition of the Verilog-A hardware description language, as proposed by the analog Technical Subcommittee of Open Verilog International (OVI), can be found in the Verilog-A Language Reference Manual (LRM). An LRM to describe mixed signal, Verilog-AMS, is in development and will be available in 1997. Several Verilog-A prototype simulators are now in development and three are available from commercial CAD tool providers. This paper contains information about Verilog-A, the motivation to develop it, some thoughts on model development, and an example of a Verilog-A module.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"100 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117310828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Functional verification with completely self-checking tests 功能验证与完全自检测试
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588525
E. Zhang, E. Yogev
{"title":"Functional verification with completely self-checking tests","authors":"E. Zhang, E. Yogev","doi":"10.1109/IVC.1997.588525","DOIUrl":"https://doi.org/10.1109/IVC.1997.588525","url":null,"abstract":"Writing thorough testbenches to verify complex systems is becoming increasingly difficult and time-consuming. This paper analyzes existing functional verification methodologies, as well as some fundamental problems of functional verification of complex systems. This paper proposes a more powerful and efficient approach for writing fully self-checking tests, using a transaction-based verification method, and concurrent programming techniques. A generic 32/spl times/32 cell-based switch fabric system is used as an example to illustrate this methodology.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114823654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A synthesis preprocessor that converts implicit style Verilog into one-hot designs 一个合成预处理器，将隐式风格Verilog转换为单热设计
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588530
M. Arnold, J. D. Shuler
{"title":"A synthesis preprocessor that converts implicit style Verilog into one-hot designs","authors":"M. Arnold, J. D. Shuler","doi":"10.1109/IVC.1997.588530","DOIUrl":"https://doi.org/10.1109/IVC.1997.588530","url":null,"abstract":"Different synthesis vendors support different subsets of Verilog. One such subset is the implicit style state machine (multiple uses of edge triggered events within an always block). With this style, one can obtain working silicon in less time because the implicit style is more like software design. Unfortunately, most synthesis vendors do not support the implicit style. To make the implicit style more accessible, a freely available synthesis preprocessor is described that converts implicit style always blocks into other equivalent Verilog, which can then be synthesized by most commercial synthesis tools. This paper discusses advantages of the implicit style, how the preprocessor translates implicit style code into a one-hot design, and why the language subset (non-blocking assignment) was chosen so that the semantics of the synthesized Verliog can agree with the simulation semantics defined by IEEE 1364.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A portable mechanism for vectorizing compiled event-driven simulation 向量化编译事件驱动仿真的可移植机制
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588535
S. Mittra
{"title":"A portable mechanism for vectorizing compiled event-driven simulation","authors":"S. Mittra","doi":"10.1109/IVC.1997.588535","DOIUrl":"https://doi.org/10.1109/IVC.1997.588535","url":null,"abstract":"This paper presents a portable mechanism for vectorization of a hardware description language (HDL) in a multiprocessing environment. Each of the functional modules in the environment is atomized and put in a centralized event queue using the dynamic event scheduling mechanism. However, during the execution phase, the set of events in a particular time instant form, what we call a 'rope' of independent events. Each of the events in a rope is simulated through the creation of an independent thread in the environment. In a multiprocessing operating system (OS) this means, depending on the availability of the processor time-slice, an independent thread created from the same process will run in parallel on different processors without any special input from the program thus ensuring a platform independent portable mechanism. As there is no direct interaction between the program and the kernel of the OS, it is possible to port the code even on a uni-processor machine without any change in the code.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A next generation diagnostic ATPG system using the Verilog HDL 使用Verilog HDL的下一代诊断ATPG系统
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588532
M.L. Lynch, S. Singer
{"title":"A next generation diagnostic ATPG system using the Verilog HDL","authors":"M.L. Lynch, S. Singer","doi":"10.1109/IVC.1997.588532","DOIUrl":"https://doi.org/10.1109/IVC.1997.588532","url":null,"abstract":"This paper presents an approach for using the Verilog Hardware Description Language (HDL) together with artificial intelligence (AI) concepts such as genetic algorithms and neural networks in a next generation diagnostic automatic test pattern generation (ATPG) system. The test generation portion of the system is composed of four basic functional elements: optimizing test proposer, simulator, unsupervised pattern classifier and evaluator. The test proposer and the evaluator are implemented using a genetic algorithm (GA). The unsupervised pattern classifier is implemented with an adaptive resonance theory (ART) neural network. The model development portion of the system is composed of three basic functional elements: netlist generator (NG), component model library (CML) and automatic model builder (AMB). The paper addresses the use of the Verilog HDL in the netlist generator, automatic model builder, component model library and simulator functions. A circuit model development process is described which allows for the creation of the good circuit model as well as the fault models necessary as part of the ATPG system.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
HDL and integrating system-level simulation technologies HDL和集成系统级仿真技术
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Pub Date : 1997-03-31 DOI: 10.1109/IVC.1997.588540
C. Ussery, K. McKinley, K. Lang, E. Komp, W. LaRue
{"title":"HDL and integrating system-level simulation technologies","authors":"C. Ussery, K. McKinley, K. Lang, E. Komp, W. LaRue","doi":"10.1109/IVC.1997.588540","DOIUrl":"https://doi.org/10.1109/IVC.1997.588540","url":null,"abstract":"System level design is a critical component of any electronics product development project. However, HDL based ASIC design has remained a distinctive and separate function within projects. With the advent of deep submicron technology, large systems and subsystems can now be placed on a single chip. This requires a closer interaction between system level design and ASIC development. The paper describes an effective methodology and technology support for integrating system level simulation techniques with HDL based simulation to provide a smooth transition between each level. We start by examining an integrated verification methodology and the use models for utilizing mixed dataflow and HDL models. We then discuss combining a model of interaction derived from the work done on the Ptolemy project with a standards based implementation approach using the Open Model Forum (OMF) standard. Finally, an example is used to highlight the effectiveness of this approach.","PeriodicalId":412366,"journal":{"name":"Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130759811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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