Proceedings of the 10th International Workshop on Network on Chip Architectures最新文献

An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip 一种高效的片上自路由无阻塞互连网络

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139546

Tripti Jain, K. Schneider, Ankesh Jain

引用次数: 7

Lightweight Emulation of Virtual Channels using Swaps 使用交换的虚拟通道的轻量级仿真

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139541

Mayank Parasar, T. Krishna

{"title":"Lightweight Emulation of Virtual Channels using Swaps","authors":"Mayank Parasar, T. Krishna","doi":"10.1145/3139540.3139541","DOIUrl":"https://doi.org/10.1145/3139540.3139541","url":null,"abstract":"Virtual Channels (VCs) are a fundamental design feature across networks, both on-chip and off-chip. They provide two key benefits - deadlock avoidance and head-of-line (HoL) blocking mitigation. However, VCs increase the router critical path, and add significant area and power overheads compared to simple wormhole routers. This is especially challenging in the era of energy-constrained many-core chips. The number of VCs required for deadlock avoidance is unavoidable, but those required for mitigating HoL depend on runtime factors such as the distribution and size of single and multi-flit packets, and their intended destinations. In some cases more VCs are beneficial, while in others they may actually harm performance, as we demonstrate. In this work, we provide a low-cost microarchitectural technique to emulate the HoL mitigation behavior of VCs inside routers, without requiring the expensive data path or control path (vc state and vc allocation) for VCs. We augment wormhole routers with the ability to do an in-place swap of blocked packets to the head of the queue. Our design (SwapNoC) can operate at low area and power specs like wormhole designs, without incurring their HoL challenges.","PeriodicalId":410968,"journal":{"name":"Proceedings of the 10th International Workshop on Network on Chip Architectures","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124340516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Performance Evaluation of Mesh-based 3D NoCs 基于网格的三维noc性能评价

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139545

Jesus Gardea, Yuho Jin, Abdel-Hameed A. Badawy, J. Cook

引用次数: 0

Thermal/Traffic Mutual-Coupling Co-simulation Platform for 3D Network-on-Chip (NoC) Designs 三维片上网络(NoC)设计的热/流量互耦联合仿真平台

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139549

A. Wu, K. Chen, Chih-Hao Chao

引用次数: 0

Improving Scalability in Thermally Resilient Hybrid Photonic-Electronic NoCs 提高热弹性混合光电子noc的可扩展性

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3146943

Keyvan Ramezanpour, Xingye Liu, P. Ampadu

引用次数: 0

Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor Kalray MPPA2处理器片上虫洞交换网络的前馈路由

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139542

B. Dinechin, Amaury Graillat

引用次数: 9

Modeling and Validation of a Mixed-Criticality NoC Router Using the IF Language 基于IF语言的混合临界NoC路由器建模与验证

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139543

Mourad Dridi, M. Lallali, S. Rubini, Frank Singhoff, J. Diguet

引用次数: 5

Intra-chip Wireless Interconnect: The Road Ahead 芯片内无线互连:未来之路

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139548

A. Ganguly, N. Mansoor, Md Shahriar Shamim, M. Ahmed, Rounak Singh Narde, Abhishek Vashist, J. Venkataraman

{"title":"Intra-chip Wireless Interconnect: The Road Ahead","authors":"A. Ganguly, N. Mansoor, Md Shahriar Shamim, M. Ahmed, Rounak Singh Narde, Abhishek Vashist, J. Venkataraman","doi":"10.1145/3139540.3139548","DOIUrl":"https://doi.org/10.1145/3139540.3139548","url":null,"abstract":"On-chip wireless interconnects have been proposed to provide energy-efficient data communication paths between cores in System-on-Chips (SoCs) in the multi and many-core era. Networks-on-Chips (NoCs) when interconnecting hundreds of cores consume large amounts of energy and suffer from high and unpredictable latency due to congestion at intermediate routers. Wireless interconnects alleviate this problem by providing direct single-hop links between distant cores in the chip. While various wireless NoC (WiNoC) architectures have been proposed and evaluated in the in the past decade this technology is not yet adopted in the mainstream industry. In order to benefit from the past decade of research in WiNoC designs a few important myths regarding wireless interconnects need to be dispelled while propelling the research to tangible technology transfer. In this paper several vectors that define the design space of WiNoCs will be identified while highlighting the state-of-the-art accomplishments in those directions by leading research groups. This will be followed by identifying the future direction that needs to be pursued to make WiNoCs a mainstream reality. At the end a few potential high-impact use-cases for wireless interconnects are discussed.","PeriodicalId":410968,"journal":{"name":"Proceedings of the 10th International Workshop on Network on Chip Architectures","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Game-based Congestion-aware Adaptive Routing (GCAR) for Proactive Thermal-aware 3D Network-on-Chip Systems 基于游戏的拥塞感知自适应路由(GCAR)，用于主动热感知3D片上网络系统

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139547

K. Chen

{"title":"Game-based Congestion-aware Adaptive Routing (GCAR) for Proactive Thermal-aware 3D Network-on-Chip Systems","authors":"K. Chen","doi":"10.1145/3139540.3139547","DOIUrl":"https://doi.org/10.1145/3139540.3139547","url":null,"abstract":"Because of the stacking dies and heterogeneous thermal conduction, the three dimensional Network-on-Chip (3D NoC) suffers from more serious thermal problem. The thermal issue limits the performance gain of 3D integration and results in lower reliability of the system. To ensure the thermal safety, the Proactive Dynamic Thermal Management (PDTM) is proven as an efficient way to mitigate the performance impact during the temperature control period. The PDTM involves the different clock frequency assignment to each NoC node based on the information of temperature prediction results. Therefore, the PDTM can early control the system temperature before the system temperature achieves the thermal emergency, which helps to mitigate the performance impact. However, due to the different clock frequency assignment, the heterogeneous packet processing speed will lead to unbalanced traffic distribution and significant performance degradation. Although many congestion-aware adaptive routing algorithms can detour the packets away from the traffic congested regions, these approaches only adopt the information of buffer congestion status to deliver the packets, which makes the packet transmission become static and results in large thermal stress in the traffic non-congested routing regions. To increase the routing path diversity during the temperature control period, we apply the Game Theory to propose a Game-based Congestion-aware Adaptive Routing (GCAR) in this paper. The GCAR will distribute the packet delivery based on the Nash Equilibrium property in Game Theory. The experimental results show that the proposed GCAR will improve 35% -- 66% system performance compared with the previous related works.","PeriodicalId":410968,"journal":{"name":"Proceedings of the 10th International Workshop on Network on Chip Architectures","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132882111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On Error Injection for NoC Platforms: A UVM-based Practical Case Study NoC平台的错误注入:基于uvm的实际案例研究

Proceedings of the 10th International Workshop on Network on Chip Architectures Pub Date : 2017-10-14 DOI: 10.1145/3139540.3139544

Sameh El-Ashry, Hala Ibrahim, M. A. Ibrahem, Mostafa Khamis, A. Shalaby, Mohamed Abdelsalam, M. El-Kharashi

{"title":"On Error Injection for NoC Platforms: A UVM-based Practical Case Study","authors":"Sameh El-Ashry, Hala Ibrahim, M. A. Ibrahem, Mostafa Khamis, A. Shalaby, Mohamed Abdelsalam, M. El-Kharashi","doi":"10.1145/3139540.3139544","DOIUrl":"https://doi.org/10.1145/3139540.3139544","url":null,"abstract":"Error injection has become critically important for testing the reliability of the hardware of any system. Measuring how a design under test reacts to different error injection methodologies is very essential for verification engineers to design dependable Universal Verification Methodology (UVM) scoreboards for error-detection purposes. The main target of this paper is to decide on the feasibility and compatibility of some error injection techniques when used with Networks-on-Chip (NoC) platforms. We target a UVM-based error injection and detection environment with its reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two example NoC components: a base router, which is a simple case study to prove proposed schemes and a configurable router, which is a complex open-source case study that provides the ability of changing the router's architecture with the change of some parameters and applied algorithms. The main novelty of our work is to integrate a full UVM environment with the various approaches of error injection and detection using reusable, generic UVM environment and components for NoC while inspecting network response according to error type and injection methodology.","PeriodicalId":410968,"journal":{"name":"Proceedings of the 10th International Workshop on Network on Chip Architectures","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6