On Error Injection for NoC Platforms: A UVM-based Practical Case Study

Abstract

Error injection has become critically important for testing the reliability of the hardware of any system. Measuring how a design under test reacts to different error injection methodologies is very essential for verification engineers to design dependable Universal Verification Methodology (UVM) scoreboards for error-detection purposes. The main target of this paper is to decide on the feasibility and compatibility of some error injection techniques when used with Networks-on-Chip (NoC) platforms. We target a UVM-based error injection and detection environment with its reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two example NoC components: a base router, which is a simple case study to prove proposed schemes and a configurable router, which is a complex open-source case study that provides the ability of changing the router's architecture with the change of some parameters and applied algorithms. The main novelty of our work is to integrate a full UVM environment with the various approaches of error injection and detection using reusable, generic UVM environment and components for NoC while inspecting network response according to error type and injection methodology.