Proceedings of International Conference on Computer Aided Design最新文献_第2页

ACV: an arithmetic circuit verifier ACV:算术电路校验器

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569822

Yirng-An Chen, R. Bryant

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引用次数: 39

Tearing based automatic abstraction for CTL model checking 基于撕裂的CTL模型自动提取

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.568969

Woohyuk Lee, Abelardo Pardo, Jaemoon Jang, G. Hachtel, F. Somenzi

引用次数: 60

Inaccuracies in power estimation during logic synthesis 逻辑合成时功率估计不准确

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569826

D. Brand, C. Visweswariah

引用次数: 38

Basic concepts for an HDL reverse engineering tool-set 一个HDL逆向工程工具集的基本概念

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569423

G. Lehmann, Bernhard Wunder, K. Müller-Glaser

引用次数: 10

Compact and complete test set generation for multiple stuck-faults 多卡故障测试集生成紧凑完整

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569601

Alok Agrawal, A. Saldanha, L. Lavagno, A. Sangiovanni-Vincentelli

引用次数: 17

Polarized observability don't cares 极化可观测性不在乎

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.5555/244522.244938

H. Arts, Michel Berkelaar, C. V. Eijk

引用次数: 0

Analytical delay models for VLSI interconnects under ramp input 斜坡输入下超大规模集成电路互连的分析延迟模型

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.568907

A. Kahng, K. Masuko, S. Muddu

引用次数: 72

Static timing analysis for self resetting circuits 自复位电路的静态时序分析

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569415

V. Narayanan, B. Chappell, B. Fleischer

{"title":"Static timing analysis for self resetting circuits","authors":"V. Narayanan, B. Chappell, B. Fleischer","doi":"10.1109/ICCAD.1996.569415","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569415","url":null,"abstract":"Static timing analysis techniques are widely used to verify the timing behavior of large digital designs implemented predominantly in conventional static CMOS. These techniques, however, are not sufficient to completely verify the dynamic circuit families now finding favor in high-performance designs. In this paper, we describe an approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-resetting CMOS (SRCMOS). Due to the circuit structure employed in SRCMOS, designs naturally decompose into a hierarchy of gates and macros; timing analysis must address and preferably exploit this hierarchy. At the gate level, three categories of constraints on pulse timing arise from considering the effects of pulse width, overlap, and collisions. Timing analysis is performed at the macro level, by a) performing timing tests at macro boundaries and b) using macro-level delay models. We define various macro-level timing tests which ensure that fundamental gate-level timing constraints are satisfied. We extend the standard delay model to handle leading and trailing edges of signal pulses, across-chip variations, trading of signals, and slow and fast operating conditions. We have developed an SRCMOS timing analyzer based on this approach; the analyzer implemented as extensions to a standard static timing analysis program, thus facilitating its integration into an existing design system and methodology.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125619679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Noise in deep submicron digital design 深亚微米数字设计中的噪声

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569906

K. Shepard, V. Narayanan

引用次数: 336

Digital sensitivity: predicting signal interaction using functional analysis 数字灵敏度:使用功能分析预测信号相互作用

Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569907

D. Kirkpatrick, A. Sangiovanni-Vincentelli

引用次数: 50