Proceedings of the 2nd IEEE Conference on Nanotechnology最新文献

Coherent LO phonons generated by high-velocity electrons in two-dimensional channels and their impact on carrier transport 二维通道中高速电子产生的相干LO声子及其对载流子输运的影响

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032107

S. Komirenko, K.W. Kim, V. Kochelap, M. Stroscio

引用次数: 1

High-fidelity modeling of nanosystems: novel methods and paradigms 纳米系统的高保真建模:新方法和范例

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032132

S. Lyshevski

引用次数: 0

Cooperativity in DNA object self assembly DNA对象自组装中的协同性

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032249

M. Norton, A. Dykes

引用次数: 0

Electronic transport and noise in nanoelectronic ballistic N/sup +/-i-N/sup +/ diodes 纳米电子弹道N/sup +/-i-N/sup +/二极管中的电子输运和噪声

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032236

G. Gomila, I. R. Cantalapiedra, T. González, L. Reggiani

引用次数: 0

Quantum-coherent transport in coupled quantum-dots 耦合量子点中的量子相干输运

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032258

J. Bird, M. Elhassan, A. Shailos, C. Prasad, D. Ferry, N. Aoki, L.-H. Lin, Y. Ochiai, K. Ishibashi, Y. Aoyagi

引用次数: 0

Fabrication of ultrahigh-density nano-pyramid arrays (NPAs) on [100] silicon wafer using scanning probe lithography and anisotropic wet etching 扫描探针光刻和各向异性湿法刻蚀在[100]硅片上制备超高密度纳米金字塔阵列(NPAs)

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032246

J. Sheu, S. P. Yeh, C.H. Wu, K. You

{"title":"Fabrication of ultrahigh-density nano-pyramid arrays (NPAs) on [100] silicon wafer using scanning probe lithography and anisotropic wet etching","authors":"J. Sheu, S. P. Yeh, C.H. Wu, K. You","doi":"10.1109/NANO.2002.1032246","DOIUrl":"https://doi.org/10.1109/NANO.2002.1032246","url":null,"abstract":"Convex and concave nano-pyramid arrays (NPAs) with an areal bit density of 64.5 Gbits/in/sup 2/ has been demonstrated by means of scanning probe lithography (SPL) and wet etching on the [100]-orientation silicon wafer. First, we investigated the use of a contact-mode atomic force microscope (AFM) in the generation of oxide patterns on silicon [100] surfaces. Subsequently, utilizing the oxide pattern as Si etching masks, the Si substrate was dipped in aqueous KOH solution, where un-oxidized regions were selectively etched by aqueous KOH orientation-dependent etching (ODE). Using this simple process, 20 nm convex NPAs with 100 nm pitch can be fabricated successfully. Similarly, about 2 nm concave NPAs with 100 nm were obtained after the oxidized samples were dipped in aqueous HF solution, the oxide regions were selectively etched away. To demonstrate the capability of this technology, we have showed an AFM micrograph of the letters \"TLS\". These patterns correspond to an ultrahigh data-storage density of about 64.5 Gbits/in/sup 2/, more than 20 times increase in areal density compared to conventional optical recording. We also demonstrated that the minimum size of the pyramids and the minimum pitch could be easily controlled by the apex size of the pyramid, that is, the size of the oxidized region by AFM-based field-induced oxidation. The results indicated that this technique has potential to provide a pathway to the higher densities that will be needed in the decades ahead. Also, the influenced parameters of oxide pattern and the influence of wet etching on etching rate and shape of etched structure will be discussed.","PeriodicalId":408575,"journal":{"name":"Proceedings of the 2nd IEEE Conference on Nanotechnology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116468534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parallelization of the nanoscale device simulator nanoMOS-2.0 using a 100 nodes linux cluster 使用100节点linux集群的纳米级设备模拟器nanoMOS-2.0的并行化

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032277

S. Goasguen, A.R. Butt, K. Colby, M.S. Lundstrorn

引用次数: 5

Arrays of nano-rings for magnetic storage applications 磁存储应用的纳米环阵列

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032125

V. Metlushko, U. Welp, V. Vlasko-Vlasov, G. Crabtree, N. Zaluzec, J. Hiller, M. Grimsditch, B. Ilic, J. Bekaert, V. Moshchalkov, Y. Bruynseraede, J. Das, J. De Boeck, G. Borghs, Xiaobin Zhu, P. Grutter

引用次数: 2

Self-propelled drop movement by manipulation of nanoscale adsorbates through molecular self-assembly 通过分子自组装操纵纳米级吸附的自推进滴运动

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032268

Jun Yang, G. Mo, Seokwon Lee, P. E. Laibinis, D. Kwok

引用次数: 1

Balancing QCA logic gates under image charge neutralization 在图像电荷中和下平衡QCA逻辑门

Proceedings of the 2nd IEEE Conference on Nanotechnology Pub Date : 2002-11-07 DOI: 10.1109/NANO.2002.1032262

J. Lusth

{"title":"Balancing QCA logic gates under image charge neutralization","authors":"J. Lusth","doi":"10.1109/NANO.2002.1032262","DOIUrl":"https://doi.org/10.1109/NANO.2002.1032262","url":null,"abstract":"Quantum-dot cellular automata (QCA) devices for computing through energy relaxation via quantum mechanical effects, promise high speed, very low power, and extremely high density. Steady progress has been made in implementing QCA; a small binary logic device has recently been manufactured and its logical switching behavior demonstrated. However, computation with hierarchical assemblies of primitive logic devices has not yet been demonstrated. Earlier work has shown that the four ground states of the originally proposed automata for implementing AND and OR are at slightly different energy levels. Because of this, certain combinations of these gates relax to ground states that encode an incorrect computation. A previously proposed construct, which essentially computes all four ground states simultaneously and thus evens out the disparities, works well under the idealized charge neutralization scheme originally proposed by the inventors of QCA. Unfortunately, under the more realistic image charge neutralization, the construction has only slightly better characteristics than the original gates and only then when the separation distance between the automaton and the metal layer generating the image charges is rather small. This paper investigates methods for evening out the disparate ground states in the presence of image charge neutralization. Previously, it was shown that the more symmetric the automaton, the better its computational behavior under image charge neutralization. It is shown that adding symmetry also reduces the disparity in ground states and a new construct for balancing QCA logic gates is presented.","PeriodicalId":408575,"journal":{"name":"Proceedings of the 2nd IEEE Conference on Nanotechnology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133150148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2