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Anti-counterfeiting, Security, and Identification最新文献

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Specifying and checking network protocol based on TLA 指定和检查基于TLA的网络协议
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325286
Liang Wan, Wenchang Shi
{"title":"Specifying and checking network protocol based on TLA","authors":"Liang Wan, Wenchang Shi","doi":"10.1109/ICASID.2012.6325286","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325286","url":null,"abstract":"Network protocol vulnerability detection is paramount to network security. Formalization provides an important way for vulnerability detection. In this paper, we apply TLA, which is a powerful tool for formal analysis, to analyze network protocols. An approach is proposed that aims to detect vulnerabilities of a protocol effectively with the TLA, with the Kerberos protocol being taken as an example. Firstly, roles for the protocol, especially those related to intruders, are created. Then actions of the roles are specified. Sessions among the roles are built. And environment parameters are set. A prototype program is developed to implement the approach, which covers the model and the detection properties of the protocol. Experiments show that our approach is effective and powerful in specifying and checking a protocol, and it is better than SPIN and SMV.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115610854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A miniaturized electronic beam-scanning phased-array antenna for radio-frequency identification (RFID) applications 用于射频识别(RFID)应用的小型化电子束扫描相控阵天线
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325343
Chih-Lin Chang, Chi-Hsing Wu, C. Tseng
{"title":"A miniaturized electronic beam-scanning phased-array antenna for radio-frequency identification (RFID) applications","authors":"Chih-Lin Chang, Chi-Hsing Wu, C. Tseng","doi":"10.1109/ICASID.2012.6325343","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325343","url":null,"abstract":"This paper presents a miniaturized electronic beam-scanning phased-array antenna for ultra-high-frequency (UHF) radio-frequency identification (RFID) applications. The developed antenna consists of two dipole antennas and a beam-scanning network, which is composed by two reflection-type phase shifters and a power divider. To reduce the fabrication cost, the circuit sizes of the beam-scanning components are miniaturized using shunt-stub-based artificial transmission lines. The measured results of the developed phased-array antenna are in good agreement with the calculated results by the antenna array theory.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127455596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improved joint correlated detection in cell search and synchronization procedure in 3GPP LTE downlink system 改进了3GPP LTE下行系统中小区搜索和同步过程中的联合相关检测
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325340
D. Lin, Jung-Cheng Hsieh, Hsin-Piao Lin
{"title":"Improved joint correlated detection in cell search and synchronization procedure in 3GPP LTE downlink system","authors":"D. Lin, Jung-Cheng Hsieh, Hsin-Piao Lin","doi":"10.1109/ICASID.2012.6325340","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325340","url":null,"abstract":"In cellular systems, user equipment (UE) must perform the cell search procedure in order to acquire symbol timing, frame timing, CFO, sector ID and group ID. In this paper, we introduce an improved frequency offset detection algorithm in Long Term Evolution (LTE) downlink systems. The detection algorithm including two steps, which are ML estimation and correlation detection. The ML estimation in order to obtains the symbol timing and fractional carrier frequency offset (CFO). We investigated two kinds of joint detection method and compared their performances. We also can acquire the sector identification (ID) and integer CFO from joint detection in the frequency domain. Simulation results demonstrate that the proposed method has better performance than conventional method. So, the proposed method is robust compared with literature method, and can effectively achieve the integer CFO and sector identification (ID).","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"475 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114888725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Study and design of a digital interphone based on dPMR446 基于dPMR446的数字对讲机的研究与设计
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325339
Chaodong Ling, Zheping Chen, Ruimin Huang
{"title":"Study and design of a digital interphone based on dPMR446","authors":"Chaodong Ling, Zheping Chen, Ruimin Huang","doi":"10.1109/ICASID.2012.6325339","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325339","url":null,"abstract":"In order to meet the need of the market and the interphone's transition from analog to digital, this paper presents the design of a digital interphone based on dPMR446 communication protocol and MELP (mixed excitation linear prediction) vocoder. The system based on the scheme of combining MCU (micro control unit) with DSP (digital signal processor) has good practicability and expansibility. The emphasis of the article is on the introduction of the overall system architecture, the design of MCU software, the section of phase locked loop in hardware circuit and the sending and receiving process. Besides, the digital baseband process including the communication protocol and the speech coding algorithm is illustrated. Realizing the digital baseband system by the DSP can not only simplify the hardware circuit, lower cost and power consumption, but also is convenient to choose different kinds of baseband processing algorithm as needed.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124657383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A multi-phase clock design for super high-speed time interleaved analog-to-digital converter 超高速时间交错模数转换器的多相时钟设计
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325291
Yuhan Gao, Yong-lu Wang, Z. Zhang
{"title":"A multi-phase clock design for super high-speed time interleaved analog-to-digital converter","authors":"Yuhan Gao, Yong-lu Wang, Z. Zhang","doi":"10.1109/ICASID.2012.6325291","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325291","url":null,"abstract":"In this paper, we present a multi-phase clock (MPC) which is used in a super high-speed time interleaved analog-to-digital converter (TI ADC). To meet the timing requirements of the whole ADC, timing design between channels must be performed carefully, meanwhile, because the signal-to-noise ratio(SNR) of the whole ADC is restrained to the time-skew and jitter performance of the multi-phase clock, lower these timing errors is very important for TI ADC. We use a shift register based multi-phase generator to implement the multiphase relationship between sub-clocks. Digital calibration of the time-skew of single channel clock and serial peripheral interface (SPI) are adopted to lower timing errors between them further more. As a demonstration, a 4-phase clock is implemented, the presented clock circuit is used in a 8bit 5Gsps TI ADC. The whole TI ADC is implemented using a 0.18μm SiGe BiCMOS process. As a result of test, the whole ADC has a SNR of about 45dB at the input frequency of 495MHZ.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129433221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and implementation of a high-voltage power supply for industrial In-mold labeling applications 为工业模内标签应用设计和实现高压电源
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325300
T. Chen, H. Chiu, Yu-Kang Lo, Wei-Lun Chen, Yan-Zhang Chen, Guan-Chi Tseng, Yu-Chen Chang
{"title":"Design and implementation of a high-voltage power supply for industrial In-mold labeling applications","authors":"T. Chen, H. Chiu, Yu-Kang Lo, Wei-Lun Chen, Yan-Zhang Chen, Guan-Chi Tseng, Yu-Chen Chang","doi":"10.1109/ICASID.2012.6325300","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325300","url":null,"abstract":"This paper designs and implements a high-voltage DC power supply with wide-range output voltage up to 30kV. There are two stages for the power conversion. The pre-stage circuit is a transition-mode (TM) power factor correction (PFC) converter for improving input power factor and providing a regulated 380V DC output. The post-stage is a DC/DC converter, to use a buck-type current-fed push-pull as its configuration; the secondary is a multiple-voltage circuit, for producing 5-30kV high voltage output. A control interface is also designed to communicate with remote control unit via controller area network (CAN) bus communication protocols. Operating principles and design considerations of the studied high-voltage power supply are discussed and analyzed. Finally, a 150W laboratory prototype was implemented and tested to verify the feasibility of the proposed scheme.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computational identification of proteins sub-network in Parkinson's disease study 帕金森病研究中蛋白质子网络的计算识别
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325320
Yue Huang, Jun Zhang, Yunying Huang
{"title":"Computational identification of proteins sub-network in Parkinson's disease study","authors":"Yue Huang, Jun Zhang, Yunying Huang","doi":"10.1109/ICASID.2012.6325320","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325320","url":null,"abstract":"Parkinson's disease (PD) is a typical case of neurodegenerative disorder, which often impairs the sufferer's motor skills, speech, and other functions. Combination of proteinprotein interaction (PPI) network analysis and gene expression studies provides a better insight of Parkinson's disease. In our work a computational approach was developed to identify protein signal network in PD study. First, a network-constrain regularization analysis is employed to the linear regression model for gene expression data from transgenic mouse models in normal and with Parkinson's disease. Proteins sub-network was then detected based on an integer linear programming model by integrating microarray data and PPI database.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC 高性能流水线ADC中低抖动时钟占空比稳定器的设计
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325310
Mingwen Zhang, Yongsheng Yin, Honghui Deng, Hongmei Chen
{"title":"Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC","authors":"Mingwen Zhang, Yongsheng Yin, Honghui Deng, Hongmei Chen","doi":"10.1109/ICASID.2012.6325310","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325310","url":null,"abstract":"This paper introduces a design of clock duty cycle stabilizer (DCS) for high-speed pipelined ADC, and analyses the internal parameters on the impact of the circuit performance. Circuit module includes programmable clock input buffer, clock synthesizer, duty cycle detection circuit and nonoverlapping clock generation circuit. The circuit and layout are achieved by 0.18 μm CMOS 1P5M Mixed Signal process. The Cadence Spectre post-simulation results show: The circuit can work for a wide frequency range from 20MHz to 250MHz; duty cycle accuracy of (50±0.25) %, in the 250MHz input frequency, the RMS jitter is 53 fs. The measured performance shows it can work with high speed, high precision and low jitter characteristics, being not strictly requirement on the input clock signal, nonoverlapping time controllable.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Empirical exploration of lattice attacks for building secure knapsack cryptosystems 构建安全背包密码系统的格攻击的经验探索
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325281
S. Jen, Chia-Yu Lu, Tse-Lin Lai, J. Yang
{"title":"Empirical exploration of lattice attacks for building secure knapsack cryptosystems","authors":"S. Jen, Chia-Yu Lu, Tse-Lin Lai, J. Yang","doi":"10.1109/ICASID.2012.6325281","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325281","url":null,"abstract":"Pending the possible realization of quantum computers, the RSA algorithm face critical challenges because of weaknesses under quantum cryptanalysis. A possible replacement may be knapsack cryptosystems, which do not yield any weaknesses to quantum computation. At present, the most significant challenge against knapsack cryptosystems is lattice attack, and public key density has historically been used to measure the security of knapsack cryptosystems against it. In this paper, we demonstrate the compromise of an acceptably dense knapsack cryptosystem using lattice attack. In order to quantify the security of knapsack cryptosystems under lattice attacks, we design experiments to analyze possible affecting factors. We demonstrate that it is not appropriate to assess the security of a knapsack cryptosystem by only considering density. Instead, there exist some other factors in literature which have more significance than density. Building on these results, we develop an empirically secure knapsack cryptosystem which explores possible directions for improving knapsack cryptosystems.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hierarchical semantic model for objectionable Web text content detection 不良Web文本内容检测的层次语义模型
Anti-counterfeiting, Security, and Identification Pub Date : 2012-10-11 DOI: 10.1109/ICASID.2012.6325325
Jiangjiao Duan, Jianping Zeng, Shiyong Zhang
{"title":"Hierarchical semantic model for objectionable Web text content detection","authors":"Jiangjiao Duan, Jianping Zeng, Shiyong Zhang","doi":"10.1109/ICASID.2012.6325325","DOIUrl":"https://doi.org/10.1109/ICASID.2012.6325325","url":null,"abstract":"Objectionable Web text content becomes popular in many web sites on the Internet recently. Since it has been shown that the kind of text content is very harmful to young children, several measures have been taken to detect the objectionable text content. Unlike current methods, a scene-based method is proposed to recognize the objectionable text with aim at improving the performance, especially in the semantic detection. A scene which is defined by a set of sentences is assigned as the topics of objectionable content. Then, a hierarchical semantic model that can describe the scene from different granularity is learnt from the sentence set. Objectionable Web text detection is performed based on the similarity between the text and the model. Experiments are done on real world text sets which come from Web forums, and the results show that the proposed method can achieve better performance than that of keyword-based method with semantic feature selection. The ability in detecting semantic objectionable text is studied by varying several key parameters of the model.","PeriodicalId":408223,"journal":{"name":"Anti-counterfeiting, Security, and Identification","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128516918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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