Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC

Abstract

This paper introduces a design of clock duty cycle stabilizer (DCS) for high-speed pipelined ADC, and analyses the internal parameters on the impact of the circuit performance. Circuit module includes programmable clock input buffer, clock synthesizer, duty cycle detection circuit and nonoverlapping clock generation circuit. The circuit and layout are achieved by 0.18 μm CMOS 1P5M Mixed Signal process. The Cadence Spectre post-simulation results show: The circuit can work for a wide frequency range from 20MHz to 250MHz; duty cycle accuracy of (50±0.25) %, in the 250MHz input frequency, the RMS jitter is 53 fs. The measured performance shows it can work with high speed, high precision and low jitter characteristics, being not strictly requirement on the input clock signal, nonoverlapping time controllable.