{"title":"Resource binding-a universal approach to parallel programming","authors":"Honda Shing, L. Ni","doi":"10.1109/SUPERC.1990.130072","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130072","url":null,"abstract":"The authors present a parallel programming paradigm, resource binding, which offers an architecture-independent environment for various parallel computation models. The resource binding technique, with a simple set of primitives, enables a flexible and consistent way of handling process synchronization, shared resource management, and other problems in parallel programming. High portability can be maintained without losing performance. For a clear introduction to the technique, comparisons are made among resource binding and other well-defined schemes such as semaphore, monitor, message passing, and Linda.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133808564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quantum molecular modeling with simulated annealing-A distributed processing and visualization application","authors":"D. Hohl, Ray Idaszak, R. O. Jones","doi":"10.1109/SUPERC.1990.130106","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130106","url":null,"abstract":"A quantum-mechanical method for calculating the geometrical structure of small molecules is presented. A combination of the density functional method with finite-temperature molecular dynamics and simulated annealing techniques provides a reliable scheme for sampling energy surfaces, without being trapped in energetically unfavorable local minima. Its value and efficiency are demonstrated by computing previously unknown geometries of small clusters composed of phosphorous, sulphur, selenium and oxygen atoms. The implementation combines distributed processing with real-time visualization and allows instantaneous interaction with the simulation. The computationally demanding quantum mechanics problem is solved on a Cray supercomputer, communicating with a Silicon Graphics Incorporated (SGI) workstation in a UNIX environment using SGI's distributed graphics library (DGL).<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133556872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A network-topology independent task allocation strategy for parallel computers","authors":"T. Baba, Y. Iwamoto, T. Yoshinaga","doi":"10.1109/SUPERC.1990.130114","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130114","url":null,"abstract":"For mapping a task graph to a processor graph, this strategy evaluates several functions that represent some intuitively feasible properties of the graphs. Several strategies are defined to guide the mapping process, utilizing the indicated values. An allocation system has been designed and implemented based on this strategy. The experimental results indicate the following: the system can yield 2.14 times better allocation than an arbitrary allocation; it is difficult to select a single strategy capable of providing the best solutions for a wide range of task-processor combinations; and the computation time of the allocator is reasonable. The effect of task and processor topology combinations on the allocation results is also discussed.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130096975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Partitioning declarative programs into communicating processes","authors":"J. M. Roy, Mark Nagel, L. Bic","doi":"10.1109/SUPERC.1990.130110","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130110","url":null,"abstract":"The Process-Oriented Dataflow System (PODS) is an execution model that combines the von Neumann and dataflow models of computation to gain the benefits of each. Central to PODS is the concept of array distribution and its effects on partitioning and mapping processes. The authors present and discuss the results of executing the classic matrix multiply algorithm (with 1024 data points) on a PODS simulator. The key result is that PODS can take advantage of the parallelism in matrix multiply using a simple automated partitioning scheme.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116722571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experimental analysis of communication/data-conditional aspects of a mixed-mode parallel architecture via synthetic computations","authors":"S. Fineberg, T. Casavant, H. Siegel","doi":"10.1109/SUPERC.1990.130080","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130080","url":null,"abstract":"Experimentation aimed at determining the potential benefit of mixed-mode SIMD/MIMD (single instruction, multiple data/multiple instruction, multiple data) parallel architectures is reported. The experimentation is based on timing measurements made on the PASM (Partitionable SIMD/MIMD) system prototype utilizing carefully coded synthetic variations of a well-known algorithm. The synthetic algorithms used to measure and evaluate this system were based on bitonic sorting of sequences stored in the processing elements. This computation was mapped to both the hybrids of the SIMD and MIMD modes. The computations were coded in these four ways and experiments were performed that explore the tradeoffs among them. The results of these experiments are presented and discussed, with special consideration of the effects of the system's architecture. The goal is to obtain implementation-independent analyses of the attributes of mixed-mode parallel processing with respect to the computational characteristics of the application being examined.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129381789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A linear array of processors with partially shared memory for parallel solution of PDE","authors":"Y. Okawa, N. Haraguchi","doi":"10.1109/SUPERC.1990.130000","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130000","url":null,"abstract":"A multiprocessor architecture with partially shared memory blocks is proposed which is suited for the successive approximation of scientific computing problems, such as matrix operations and partial differential equations. The topology is a ring, but the system configuration is a subset of an orthogonal multiprocessor that I.D. Scherson (1989) and K. Hwang (1989) have already proposed. An experimental system was built which was used to solve a heat-conduction problem. The computing time is about 600 s in the case of 256*256 grid points.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133466327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Baba, Tsutomu Yoshinaga, T. Iijima, Y. Iwamoto, Masahiro Hamada, Mitsuru Suzuki
{"title":"A parallel object-oriented total architecture: A-NET","authors":"T. Baba, Tsutomu Yoshinaga, T. Iijima, Y. Iwamoto, Masahiro Hamada, Mitsuru Suzuki","doi":"10.1109/SUPERC.1990.130031","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130031","url":null,"abstract":"A-NET is a parallel object-oriented total architecture for highly parallel computation. Starting with a computation model, the authors describe parallel constructs of the designed language, called A-NETL; the A-NETL-oriented machine instruction set architecture; the hardware organization of a node processor, which consists of a 40-bit processing element and a router; and a local operating system on each of the node processors. Statistics for the designed language and the machine are derived from experimental results.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116669249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation machine paradigm for parallel programming","authors":"Manohar Rao, Z. Segall, D. Vrsalovic","doi":"10.1109/SUPERC.1990.130074","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130074","url":null,"abstract":"An approach for efficiently mapping parallel applications onto parallel MIMD machine architectures is introduced. The applicability of this approach to uniform memory-access multiprocessors is demonstrated. It is shown that an intermediate layer of abstraction between the application level and the parallel architecture level is conducive not only to a better software productivity but also to performance efficient programs. The intermediate layer consists of a set of commonly used parallel programming paradigms (implementation machines). A mathematical representation and a pragmatic representation are provided for each implementation machine (IM). The user maps the application onto one or a set of IMs and the system implements the IMs efficiently on the underlying parallel machine.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125066314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logarithmic time cost optimal parallel sorting is not yet fast in practice","authors":"L. Natvig","doi":"10.1109/SUPERC.1990.130059","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130059","url":null,"abstract":"It is pointed out that, when looking for new and faster parallel sorting algorithms for use in massively parallel systems it is tempting to investigate promising alternatives from the large body of research done on parallel sorting in the field of theoretical computer science. It is shown how this kind of investigation can be done on a simple but versatile environment for programming and measuring of PRAM (parallel random access machine) algorithms. The practical value of Cole's parallel merge sort algorithm has been investigated by comparing it with Batcher's bitonic sorting. The O(log n) time consumption of Code's algorithm implies that it must be faster than bitonic sorting which is o(log/sup 2/ n) time, if n is large enough. However, it has been found that bitonic sorting is faster as long as n is less than 1.2*10/sup 21/. Consequently, it is concluded that Cole's logarithmic time algorithm is not fast in practice.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128789215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Uni-directional hypercubes","authors":"Chih-Hsiang Chou, D. Du","doi":"10.1109/SUPERC.1990.130028","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130028","url":null,"abstract":"Two unidirectional hypercube topologies are proposed. Both have short diameter, short average distance, efficient routing, and multiple paths characteristics, and can accommodate a large number of nodes. They simplify the communication port hardware from bidirectional to unidirectional, and hence allow one to build larger VLSI hypercubes as well as to implement hypercube-based MANs (metropolitan area networks) with optical fibers. Improvements to and optimizations of the proposed schemes are discussed.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129773014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}