{"title":"Perfect Benchmarks decomposition and performance on VAX multiprocessors","authors":"Z. Cvetanovic, E. Freedman, C. Nofsinger","doi":"10.1109/SUPERC.1990.130055","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130055","url":null,"abstract":"The authors present the methods for decomposition and the performance of the Perfect Benchmark suite on two VAX multiprocessors. Results indicate that it was possible to obtain significant performance gains on both VAX multiprocessors, relative to a uniprocessor case. A methodology that can be applied to decompose other existing scientific and engineering applications is proposed. Guidelines for autodecomposing compiler improvements are provided. The authors discuss and quantify the effect of different cache designs on the multiprocessor performance.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133899666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"UC: a language for the connection machine","authors":"R. Bagrodia, K. Chandy, E. Kwan","doi":"10.1109/SUPERC.1990.130064","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130064","url":null,"abstract":"In designing parallel languages, the concern for defining a simple virtual machine must be balanced against the need to efficiently map a program on a specific architecture. UC addresses this problem by separating the programming task from efficiency considerations. UC programs are designed using a small set of constructs that include reduction, parallel assignment, and fixed-point computation. The language also provides a map section that may optionally be used by a programmer to specify data mappings for the program. The authors describe the UC constructs and their implementation on the Connection Machine. They also present measurements of the compiler for simple benchmarks.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scan primitives for vector computers","authors":"S. Chatterjee, G. Blelloch, Marco Zagha","doi":"10.1109/SUPERC.1990.130084","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130084","url":null,"abstract":"The authors describe an optimized implementation of a set of scan (also called all-prefix-sums) primitives on a single processor of a CRAY Y-MP, and demonstrate that their use leads to greatly improved performance for several applications that cannot be vectorized with existing computer technology. The algorithm used to implement the scans is based on an algorithm for parallel computers. A set of segmented versions of these scans is only marginally more expensive than the unsegmented versions. The authors describe a radix sorting routine based on the scans that is 13 times faster than a Fortran version and within 20% of a highly optimized library sort routine, three operations on trees that are between 10 to 20 times faster than the corresponding C versions, and a connectionist learning algorithm that is 10 times faster than the corresponding C version for sparse and irregular networks.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115214988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cost-performance analysis of heterogeneity in supercomputer architectures","authors":"D. Menascé, Virgílio A. F. Almeida","doi":"10.1109/SUPERC.1990.130017","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130017","url":null,"abstract":"The cost-performance of heterogeneity in supercomputer architectures is analyzed. Queuing models are used to study the performance of homogeneous and heterogeneous supercomputer models. Grosch's law, which states that computer performance increases as the square of its cost, is used to analyze cost aspects of the models. It is concluded that heterogeneity in supercomputer architectures is a quite promising design approach that deserves further investigation.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123398923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving instruction cache behavior by reducing cache pollution","authors":"Rajiv Gupta, Chi-Hung Chi","doi":"10.1109/SUPERC.1990.130005","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130005","url":null,"abstract":"Compiler techniques for improving instruction cache performance are described. Through repositioning of the code in the main memory, leaving memory locations unused, code duplication, and code propagation, the effectiveness of the cache can be improved due to reduced cache pollution and fewer cache misses. Results of experiments indicate that significant reduction in bus traffic results from the use of these techniques. Since memory bandwidth is a critical resource in shared memory multiprocessors, such systems can benefit from the techniques described. The notion of control dependence is used to decide when instructions belonging to different basic blocks can be allowed to share the same cache line without increasing cache pollution.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131179444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallel program debugging with on-the-fly anomaly detection","authors":"R. Hood, K. Kennedy, J. Mellor-Crummey","doi":"10.1109/SUPERC.1990.130004","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130004","url":null,"abstract":"An approach for parallel debugging that coordinates static analysis with efficient on-the-fly access anomaly detection is described. On-the-fly instrumentation mechanisms are being developed for the structured synchronization primitives of Parallel Computing Forum (PCF) Fortran, the emerging standard for parallel Fortran. The proposed instrumentation techniques guarantee that one can isolate schedule-dependent behavior in a schedule-independent fashion. The result is that a single-instrumented execution will either report sources of schedule-dependent behavior, or it will validate that all executions of the program on the same data compute the same result. When an instrumented execution is being used solely to find sources of schedule-dependent behavior, its cost can be reduced by slicing out computations that do not contribute to race conditions. Ongoing efforts to incorporate the proposed debugging approach in the ParaScope environment are described.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123075686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computer simulation of high-speed impact response of composites","authors":"S. Langlie, W. Cheng, I. Dilber","doi":"10.1109/SUPERC.1990.130107","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130107","url":null,"abstract":"The authors share some of their experiences with the use of a supercomputer to facilitate the analysis and design of high-velocity impact processes in composite systems. They also discuss the benefits of color animation of the results on a MacIntosh computer. The calculations were carried out on a CRAY-2 using an impact model developed for high-velocity impact/penetration of fiber-reinforced layered composites. The model is built on a continuum approach and includes a basic orthotropic constitutive material behavior. A computer program was developed to convert the results of the analysis for hundreds of time steps into 8-bit raster images and these are animated using graphic tools developed at NCSA. The same set of images were also directly recorded on a video tape. A fifteen-times improvement in speed has been recorded on the CRAY-2 over a VAX 8600 computer previously used for the same calculations.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116969438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architectural support for register allocation in the presence of aliasing","authors":"Ben Heggy, M. Soffa","doi":"10.1109/SUPERC.1990.130093","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130093","url":null,"abstract":"A hardware support mechanism is presented that permits all classes of data objects, including dynamically allocated objects and array elements, to be held in registers without consideration of possible aliases and without requiring that the generated code maintain consistency between register and memory copies of variables. Use of this approach permits programs to benefit from the speed advantages and reduced memory traffic associated with register storage, obviates the need to collect aliasing information for use in register allocation, and reduces instruction traffic by eliminating code used solely to maintain register-memory consistency. The support hardware can be implemented using known hardware technology and without increasing the cycle time of the processor.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117176185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallelization of loops with exits on pipelined architectures","authors":"P. Tirumalai, Meng Lee, M. Schlansker","doi":"10.1109/SUPERC.1990.130021","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130021","url":null,"abstract":"Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. It is shown that a broader class of loops-repeat-until, while, and loops with more than one exit-where the trip count is not known beforehand, can also be overlapped efficiently on multiple issue pipelined machines. Special features that are required in the architecture as well as compiler representations for accelerating these loop constructions are discussed. The approach uses hardware architectural support, program transformation techniques, performance bounds calculations, and scheduling heuristics. Performance results are presented for a few select examples. A prototype scheduler is currently under construction for the Cydra 5 directed dataflow computer.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122620446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A taxonomy of concepts for evaluating chess strength","authors":"H. Berliner, D. Kopec, E. Northam","doi":"10.1109/SUPERC.1990.130039","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130039","url":null,"abstract":"The authors present a taxonomy of positions in chess that require special knowledge. The taxonomy drives the selection of positions, not vice-versa. The authors present a set of annotated example problems from two specific categories that require understanding of critical concepts to achieve the maximum result.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123748647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}