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Proceedings SUPERCOMPUTING '90最新文献

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Experience with interprocedural analysis of array side effects 具有阵列副作用的程序间分析经验
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130123
P. Havlak, K. Kennedy
{"title":"Experience with interprocedural analysis of array side effects","authors":"P. Havlak, K. Kennedy","doi":"10.1109/SUPERC.1990.130123","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130123","url":null,"abstract":"The authors describe an implementation of regular section analysis in the Rice Parallel Fortran Converter (PFC), an automatic parallelization system. The overriding concern in the implementation is that it be efficient enough to be incorporated in a practical compilation system. This implementation of regular section analysis describes interprocedural side effects on subarrays in a form useful to dependence analysis while avoiding the complexity of prior solutions. The authors also examine the performance of regular section analysis on two benchmarks: the LINPACK library of linear algebra subroutines and the Rice Compiler Evaluation Program Suite, a set of complete application codes from a variety of scientific disciplines. It is demonstrated that regular section analysis is an effective means of discovering parallelism, given programs written in an appropriately modular programming style.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125535523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches 一个写更新缓存一致性协议，用于基于min的多处理器，具有基于可访问性的分割缓存
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130068
Mazin S. Algudady, C. Das, M. J. Thazhuthaveetil
{"title":"A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches","authors":"Mazin S. Algudady, C. Das, M. J. Thazhuthaveetil","doi":"10.1109/SUPERC.1990.130068","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130068","url":null,"abstract":"The authors present a cache coherence protocol for MIN-based multiprocessors with two distinct private caches: private-block caches containing information private to a processor and shared-block caches containing data accessible by all processors. The protocol utilizes a coherence control bus (snooping) for connecting all shared-block cache controllers. Timing problems due to variable transit delay through the MIN are dealt with by introducing transient states in the protocol. Assuming homogeneity of all nodes, a single-node queuing model is developed to analyze the system performance. This model is solved using the mean-value-analysis technique with protocol state probabilities, and few communication delays as input parameters. System performance measures are verified through simulation.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129355785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Efficient parallel logic simulation techniques for the Connection Machine 连接机的高效并行逻辑仿真技术
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130076
M. Chung, Yunmo Chung
{"title":"Efficient parallel logic simulation techniques for the Connection Machine","authors":"M. Chung, Yunmo Chung","doi":"10.1109/SUPERC.1990.130076","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130076","url":null,"abstract":"Three efficient parallel logic simulation techniques for the Connection Machine are developed. The first technique which uses a global clock, is a synchronous version of a traditional simulation technique. The second technique is a hybrid of both the synchronous simulation technique with a global clock and the Chandy-Misra algorithm for asynchronous event processing. The third technique, called a simulation time lookahead technique, is proposed to make the second technique more optimistic than the Chandy-Misra algorithm by predicting in advance the timestamp of the next event. Experimental results show that the three techniques achieve better performance than the Time Warp protocol on the Connection Machine. The proposed techniques are several hundred times faster than the VHDL simulator on a SUN3, especially for circuits with very large number of gates.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124652973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Chess and supercomputers: details about optimizing Cray Blitz 国际象棋和超级计算机:关于优化克雷闪电战的细节
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130041
R. Hyatt, H. Nelson
{"title":"Chess and supercomputers: details about optimizing Cray Blitz","authors":"R. Hyatt, H. Nelson","doi":"10.1109/SUPERC.1990.130041","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130041","url":null,"abstract":"The authors describe the architectural features that Cray Blitz uses to search approximately 200000 chess positions per second. They also describe the programming and algorithmic changes required to take advantage of each of several architectural features of the Cray family of computer systems.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123819300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Architecture and implementation of a VLIW supercomputer VLIW超级计算机的体系结构与实现
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130118
R. Colwell, W. E. Hall, C. Joshi, D. Papworth, P. Rodman, James E. Tornes
{"title":"Architecture and implementation of a VLIW supercomputer","authors":"R. Colwell, W. E. Hall, C. Joshi, D. Papworth, P. Rodman, James E. Tornes","doi":"10.1109/SUPERC.1990.130118","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130118","url":null,"abstract":"Very-long-instruction-word (VLIW) computers achieve high performance by exploiting the fine-grain parallelism present in sequential or vectorizable code. Multiflow's /200 and /300 VLIW systems yielded near-supercomputer performance by this means despite the relatively slow (65 ns) clocks. With its much faster clock period (15 ns) and architectural improvements, the new /500 system attains approximately 4-9* the performance of its predecessors. The authors describe the /500 architecture and implementation (i.e. TRACE/500), with special attention paid to the tradeoffs involved in designing very-high-speed VLIWs.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
A flexible communication abstraction for nonshared memory parallel computing 面向非共享内存并行计算的灵活通信抽象
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130073
G. Alverson, W. Griswold, D. Notkin, L. Snyder
{"title":"A flexible communication abstraction for nonshared memory parallel computing","authors":"G. Alverson, W. Griswold, D. Notkin, L. Snyder","doi":"10.1109/SUPERC.1990.130073","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130073","url":null,"abstract":"It is shown how a communication abstraction called the port ensemble can simplify the handling of boundary conditions and the efficient porting of programs. A port ensemble provides an explicit interface between computation and communication descriptions, thus separating the communication structure from the details of local computation and from the compiler. Port ensembles structure ports, symbolic names to and from which process can write and read values. To simplify the expression of boundary conditions, ports can be bound not only to ports on other processors, but also to nonexistent neighbors (along the edge of the computation) using special objects that represent and implement constants, variables, and arbitrary functions. Port ensembles also provide direct access to the communication structure, which simplifies changing the structure to one appropriate for a new target architecture.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131402238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
P3D: A Lisp-based format for representing general 3D models P3D:用于表示一般3D模型的基于lisp的格式
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130099
Joel S. Welling, Chris Nuuja, P. Andrews
{"title":"P3D: A Lisp-based format for representing general 3D models","authors":"Joel S. Welling, Chris Nuuja, P. Andrews","doi":"10.1109/SUPERC.1990.130099","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130099","url":null,"abstract":"The primary design goal for P3D has been to produce a metafile format which can support the needs of scientific visualization while remaining compatible with a wide range of common renderers. To this end, rendering features which are available on only a few renderers and cannot easily be emulated have been excluded from P3D. P3D is based on the Common Lisp programming language with a small number of extensions for the description of geometry. The programmability of P3D greatly eases the task of adapting existing model generators to produce P3D, in the same fashion that the programmability of the Postscript page description language eases the task of modifying code to generate Postscript. Further, programmability allows knowledge of the particular scientific domain of the model to be incorporated into the metafile. This method provides easy representation of directed acyclic graphs and complete programmability to facilitate interfaces to new model generators, without the introduction of a new and unfamiliar language.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115690725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Delirium: an embedding coordination language 谵妄:一种嵌入协调语言
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130063
S. Lucco, O. Sharp
{"title":"Delirium: an embedding coordination language","authors":"S. Lucco, O. Sharp","doi":"10.1109/SUPERC.1990.130063","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130063","url":null,"abstract":"The authors outline a strategy for expressing coordination of sequential subcomputations, realized in the embedding language Delirium. In contrast to existing embedded languages, the notation clearly expresses the coordination framework of the application. All the coordination required to execute the program is expressed in a unified Delirium program. The program contains the computational code in the form of embedded operators, written using conventional tools. The proposed environment, which executes on a variety of shared-memory multi processors, provides tools which make it possible to develop parallel applications quickly. It supports a coordination model than can guarantee deterministic execution. Programmers who remain within the restrictions of the model can develop a program on a sequential machine and be certain that it will execute deterministically on a variety of parallel architectures.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128306101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A high-performance, memory-based interconnection system for multicomputer environments 用于多计算机环境的高性能、基于内存的互连系统
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130033
C. Maples
{"title":"A high-performance, memory-based interconnection system for multicomputer environments","authors":"C. Maples","doi":"10.1109/SUPERC.1990.130033","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130033","url":null,"abstract":"The design and operation of a very-high-performance, memory-mapped interconnection system called Merlin is discussed. The design can be effectively utilized to interconnect processors in a wide variety of environments, ranging from closely-coupled, dedicated systems to distributed workstations. The system provides a uniform approach to parallel programming which is independent of interconnection topology, processing elements, and languages. By using dynamically mapped reflective memory, the system can support selectively shared virtual memory regions. This approach permits user-selected information to be shared at high speeds and low latency. There is no software involvement in the actual sharing of information, and the system overlaps computation and communication automatically, word-by-word, to the extent possible.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A semi distributed task allocation strategy for large hypercube supercomputers 大型超立方体超级计算机的半分布式任务分配策略
Proceedings SUPERCOMPUTING '90 Pub Date : 1990-11-12 DOI: 10.1109/SUPERC.1990.130116
I. Ahmad, A. Ghafoor
{"title":"A semi distributed task allocation strategy for large hypercube supercomputers","authors":"I. Ahmad, A. Ghafoor","doi":"10.1109/SUPERC.1990.130116","DOIUrl":"https://doi.org/10.1109/SUPERC.1990.130116","url":null,"abstract":"The authors present a semi-distributed approach for task scheduling in large parallel and distributed systems which is different from the conventional centralized and fully distributed approaches. The proposed strategy partitions the system into independent regions (spheres) centered at some control points. The central points, called schedulers optimally schedule tasks within their spheres and maintain state information with low overhead. The authors consider hypercube systems for evaluation and, using their algebraic characteristics, show that identification of spheres and their scheduling points is an NP-complete problem. The performance of the proposed strategy was evaluated and compared with an efficient fully distributed strategy. In addition to yielding high performance in terms of response time, better resource utilization, and throughput, the proposed strategy is shown to incur small overhead in terms of network traffic.<<ETX>>","PeriodicalId":408163,"journal":{"name":"Proceedings SUPERCOMPUTING '90","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127977881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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