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Work-in-Progress: Real-Time Containers for Large-Scale Mixed-Criticality Systems 在制品:大规模混合临界系统的实时容器
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00046
M. Cinque, G. Tommasi
{"title":"Work-in-Progress: Real-Time Containers for Large-Scale Mixed-Criticality Systems","authors":"M. Cinque, G. Tommasi","doi":"10.1109/RTSS.2017.00046","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00046","url":null,"abstract":"This paper presents the notion of real-time containers, or rt-cases, conceived as the convergence of software container technologies, such as Linux Containers and/or Docker, and real-time operating systems. The idea is to allow critical containers, characterized by stringent timeliness and reliability requirements, to cohabit with traditional non real-time containers on the same hardware. The approach allows to keep the advantages of real-time virtualization, largely adopted in the industry, while reducing its inherent scalability limitation when to be applied to large-scale mixed-criticality systems. The paper provides a reference architecture scheme for implementing the real-time container concept on top on a patched real-time Linux kernel, and it overviews the challenges to be faced to implement the rt-case vision.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123033661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Jitter-Compensated VHT and Its Application to WSN Clock Synchronization 抖动补偿VHT及其在WSN时钟同步中的应用
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00033
F. Terraneo, Fabiano Riccardi, A. Leva
{"title":"Jitter-Compensated VHT and Its Application to WSN Clock Synchronization","authors":"F. Terraneo, Fabiano Riccardi, A. Leva","doi":"10.1109/RTSS.2017.00033","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00033","url":null,"abstract":"Accurate and energy-efficient clock synchronization is an enabler for many applications of Wireless Sensor Networks. A fine-grained synchronization is beneficial both at the system level, for example to favor deterministic radio protocols, and at the application level, when network-wide event timestamping is required. However, there is a tradeoff between the resolution of a WSN node’s timekeeping device and its energy consumption. The Virtual High-resolution Timer (VHT) is an innovative solution, that was proposed to overcome this tradeoff. It combines a high-resolution oscillator to a low-power one, turning off the former when not needed. In this paper we improve VHT by first identifying the jitter of the low-power oscillator as the current limit to the technique, and then proposing an enhanced solution that synchronizes the fast and the slow clock, rejecting the said jitter. The improved VHT is also less demanding than the original technique in terms of hardware resources. Experimental results show the achieved advantages in terms of accuracy.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Network Scheduling for Secure Cyber-Physical Systems 安全网络物理系统的网络调度
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00012
Vuk Lesi, Ilija Jovanov, M. Pajic
{"title":"Network Scheduling for Secure Cyber-Physical Systems","authors":"Vuk Lesi, Ilija Jovanov, M. Pajic","doi":"10.1109/RTSS.2017.00012","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00012","url":null,"abstract":"Existing design techniques for providing security guarantees against network-based attacks in cyber-physical systems (CPS) are based on continuous use of standard cryptographic tools to ensure data integrity. This creates an apparent conflict with common resource limitations in these systems, given that, for instance, lengthy message authentication codes (MAC) introduce significant overheads. We present a framework to ensure both timing guarantees for real-time network messages and Quality-of-Control (QoC) in the presence of network-based attacks. We exploit physical properties of controlled systems to relax constant integrity enforcement requirements, and show how the problem of feasibility testing of intermittently authenticated real-time messages can be cast as a mixed integer linear programming problem. Besides scheduling a set of real-time messages with predefined authentication rates obtained from QoC requirements, we show how to optimally increase the overall system QoC while ensuring that all real-time messages are schedulable. Finally, we introduce an efficient runtime bandwidth allocation method, based on opportunistic scheduling, in order to improve QoC. We evaluate our framework on a standard benchmark designed for CAN bus, and show how an infeasible message set with strong security guarantees can be scheduled if dynamics of controlled systems are taken into account along with real-time requirements.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128286395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
On Using GEV or Gumbel Models When Applying EVT for Probabilistic WCET Estimation 应用EVT进行概率WCET估计时使用GEV或Gumbel模型
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00028
Karila Palma Silva, Luis Fernando Arcaro, R. S. Oliveira
{"title":"On Using GEV or Gumbel Models When Applying EVT for Probabilistic WCET Estimation","authors":"Karila Palma Silva, Luis Fernando Arcaro, R. S. Oliveira","doi":"10.1109/RTSS.2017.00028","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00028","url":null,"abstract":"The technique known as Measurement-Based Probabilistic Timing Analysis (MBPTA) promises producing Worst-Case Execution Time (WCET) bounds for real-time systems' tasks based on the analysis of execution time measurements through Extreme Value Theory (EVT), a statistical framework designed to estimate the probability of extreme events. For that MBPTA requires the analysed tasks' maximum observed execution times to adhere to an extreme value distribution, such as Gumbel or Generalized Extreme Value (GEV), and allows determining execution time values expected to be exceeded only with arbitrarily small probabilities. Several works on the area assume that the Gumbel model should be employed in such analysis, while others consider GEV, which generalizes Weibull, Gumbel and Fréchet models, would be more adequate. In this work we perform an empirical assessment on the reliability and tightness of the WCET bounds determined through the GEV and Gumbel models. We do so by comparing the yielded estimates and their associated confidence intervals against the maximum values observed on large samples (e.g. of size 100 million), of both real and synthetic nature, as the modelling sample size is increased.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Work-in-Progress: Adaptive Scheduling with Approximate Computing for Audio Graphs 在制品:音频图近似计算的自适应调度
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00045
P. Donat-Bouillud, C. Kirsch
{"title":"Work-in-Progress: Adaptive Scheduling with Approximate Computing for Audio Graphs","authors":"P. Donat-Bouillud, C. Kirsch","doi":"10.1109/RTSS.2017.00045","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00045","url":null,"abstract":"Interactive music systems are highly dynamic systems that combine audio processing and control in real-time. They often have to work on soft real-time platforms, where no stringent real-time guarantees can be upheld. We present here an overhead-aware online degradation algorithm that finds a tradeoff between quality and lateness for the processing nodes of a dynamic audio graph.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128908006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work-in-Progress: Design-Space Exploration of Multi-Core Processors for Safety-Critical Real-Time Systems 正在进行的工作:安全关键实时系统多核处理器的设计空间探索
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00040
Dolly Sapra, S. Altmeyer
{"title":"Work-in-Progress: Design-Space Exploration of Multi-Core Processors for Safety-Critical Real-Time Systems","authors":"Dolly Sapra, S. Altmeyer","doi":"10.1109/RTSS.2017.00040","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00040","url":null,"abstract":"In this paper we outline Design Space Exploration methodology aimed at homogeneous multi-core architectures, where the safety-criticality is the crux of a system design. Multi-core architectures provide better computational abilities, but at the same time complicate the computation of timing bounds. Determining suitable architectures that achieve timing requirements is an important aspect for a system designer. The proposed work conceptualizes ways to automate and explore different design facets of a multi-core processor. The intention is to ensure that the particular application meets its deadlines, while optimizing other objectives such as minimizing hardware costs, energy consumption and floor area. The automated exploration builds upon Mulitcore Response Time Analysis for timing verification and multicube for heuristic search methods. The aim is to generate an architecture design in the end that can be used directly to build a custom application specific processor.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132331993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Work-in-Progress: A Flexible Router Architecture for 3D NoCs 正在进行的工作:用于3D noc的灵活路由器架构
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00044
Mostafa Khamis, Mostafa Said, A. Shalaby
{"title":"Work-in-Progress: A Flexible Router Architecture for 3D NoCs","authors":"Mostafa Khamis, Mostafa Said, A. Shalaby","doi":"10.1109/RTSS.2017.00044","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00044","url":null,"abstract":"Flexibility either in buffering or routing is a very promising solution for NoC congestion problem. In this paper, a new 3D router with flexible architecture is introduced and validated for 3D NoCs. In fact, the Flexible router architecture introduced in literature would be deadlock prone if it is incorporated in a 3D NoC domain. We successfully design the new buffering constraints and extensively evaluate its performance under various traffic scenarios using real benchmark applications. We show the great enhancement of the new candidate router architecture in comparison to the conventional 3D NoC router architecture. Finally, we show that this enhancement in performance comes at a very low impact in power and area; especially for large NoC sizes.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114600261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Abstract PRET Machines 摘要PRET机
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00041
Edward A. Lee, J. Reineke, Michael Zimmer
{"title":"Abstract PRET Machines","authors":"Edward A. Lee, J. Reineke, Michael Zimmer","doi":"10.1109/RTSS.2017.00041","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00041","url":null,"abstract":"Prior work has shown that it is possible to design microarchitectures called PRET machines that deliver precise and repeatable timing of software execution without sacrificing performance. That prior work provides specific designs for PRET microarchitectures and compares them against conventional designs. This paper defines a class of microarchitectures called abstract PRET machines (APMs) that capture the essential temporal properties of PRET machines. We show that APMs deliver deterministic timing with no loss of performance for a family of real-time problems consisting of sporadic event streams with deadlines equal to periods. On the other hand, we observe a tradeoff between deterministic timing and the ability to meet deadlines for sporadic event streams with constrained deadlines.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116041443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Work-in-Progress: Cache-Aware Partitioned EDF Scheduling for Multi-core Real-Time Systems 正在进行的工作:多核实时系统的缓存感知分区EDF调度
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00054
Zhishan Guo, Y. Zhang, Lingxiang Wang, Zhenkai Zhang
{"title":"Work-in-Progress: Cache-Aware Partitioned EDF Scheduling for Multi-core Real-Time Systems","authors":"Zhishan Guo, Y. Zhang, Lingxiang Wang, Zhenkai Zhang","doi":"10.1109/RTSS.2017.00054","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00054","url":null,"abstract":"As the number of cores and utilization of the system are increasing quickly, shared resources like caches are interfering tasks' execution behaviors more heavily. In order to achieve resource efficiency in both temporal and spatial domains for multi-core real-time systems, caches should be taken into consideration when performing partitions. In this paper, partitioned Earliest Deadline First (EDF) scheduling on a preemptive multi-core platform is considered. We propose a new system model that covers inter-task cache interference and describe some ongoing work in identifying proper partition schemes under such settings.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123932149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Revisiting GPC and AND Connector in Real-Time Calculus 回顾实时微积分中的GPC和and连接器
2017 IEEE Real-Time Systems Symposium (RTSS) Pub Date : 2017-12-01 DOI: 10.1109/RTSS.2017.00031
Yue Tang, Nan Guan, Weichen Liu, L. T. Phan, W. Yi
{"title":"Revisiting GPC and AND Connector in Real-Time Calculus","authors":"Yue Tang, Nan Guan, Weichen Liu, L. T. Phan, W. Yi","doi":"10.1109/RTSS.2017.00031","DOIUrl":"https://doi.org/10.1109/RTSS.2017.00031","url":null,"abstract":"Real-Time Calculus (RTC) is a powerful framework for modeling and worst-case performance analysis of networked systems. GPC and AND are two fundamental components in RTC, which model priority-based resource arbitration and synchronization operations, respectively. In this paper, we revisit GPC and AND. For GPC, we develop tighter output arrival curves to more precisely characterize the output event streams. For AND, we first identify a problem in the existing analysis method that may lead to negative values in the output curves, and present corrections to the problem. Then we generalize AND to synchronize more than two input event streams. We implement our new theoretical results and conduct experiments to evaluate their performance. Experiment results show significant improvement of our new methods in analysis precision and efficiency.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115125793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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