{"title":"正在进行的工作:用于3D noc的灵活路由器架构","authors":"Mostafa Khamis, Mostafa Said, A. Shalaby","doi":"10.1109/RTSS.2017.00044","DOIUrl":null,"url":null,"abstract":"Flexibility either in buffering or routing is a very promising solution for NoC congestion problem. In this paper, a new 3D router with flexible architecture is introduced and validated for 3D NoCs. In fact, the Flexible router architecture introduced in literature would be deadlock prone if it is incorporated in a 3D NoC domain. We successfully design the new buffering constraints and extensively evaluate its performance under various traffic scenarios using real benchmark applications. We show the great enhancement of the new candidate router architecture in comparison to the conventional 3D NoC router architecture. Finally, we show that this enhancement in performance comes at a very low impact in power and area; especially for large NoC sizes.","PeriodicalId":407932,"journal":{"name":"2017 IEEE Real-Time Systems Symposium (RTSS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Work-in-Progress: A Flexible Router Architecture for 3D NoCs\",\"authors\":\"Mostafa Khamis, Mostafa Said, A. Shalaby\",\"doi\":\"10.1109/RTSS.2017.00044\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Flexibility either in buffering or routing is a very promising solution for NoC congestion problem. In this paper, a new 3D router with flexible architecture is introduced and validated for 3D NoCs. In fact, the Flexible router architecture introduced in literature would be deadlock prone if it is incorporated in a 3D NoC domain. We successfully design the new buffering constraints and extensively evaluate its performance under various traffic scenarios using real benchmark applications. We show the great enhancement of the new candidate router architecture in comparison to the conventional 3D NoC router architecture. Finally, we show that this enhancement in performance comes at a very low impact in power and area; especially for large NoC sizes.\",\"PeriodicalId\":407932,\"journal\":{\"name\":\"2017 IEEE Real-Time Systems Symposium (RTSS)\",\"volume\":\"148 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Real-Time Systems Symposium (RTSS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTSS.2017.00044\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Real-Time Systems Symposium (RTSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTSS.2017.00044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Work-in-Progress: A Flexible Router Architecture for 3D NoCs
Flexibility either in buffering or routing is a very promising solution for NoC congestion problem. In this paper, a new 3D router with flexible architecture is introduced and validated for 3D NoCs. In fact, the Flexible router architecture introduced in literature would be deadlock prone if it is incorporated in a 3D NoC domain. We successfully design the new buffering constraints and extensively evaluate its performance under various traffic scenarios using real benchmark applications. We show the great enhancement of the new candidate router architecture in comparison to the conventional 3D NoC router architecture. Finally, we show that this enhancement in performance comes at a very low impact in power and area; especially for large NoC sizes.