2017 Formal Methods in Computer Aided Design (FMCAD)最新文献_第3页

Column-wise verification of multipliers using computer algebra 用计算机代数对乘数进行列式验证

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102237

Daniela Ritirc, Armin Biere, Manuel Kauers

引用次数: 53

Sampling invariants from frequency distributions 频率分布的采样不变量

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102247

Grigory Fedyukovich, Samuel J. Kaufman, R. Bodík

引用次数: 34

Factored boolean functional synthesis 因式布尔泛函合成

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102250

L. M. Tabajara, Moshe Y. Vardi

引用次数: 18

FAR-Cubicle — A new reachability algorithm for Cubicle 远隔间-一种新的隔间可达性算法

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102256

S. Conchon, A. Goel, S. Krstic, R. Majumdar, Mattias Roux

引用次数: 3

Theta: A framework for abstraction refinement-based model checking Theta:用于基于抽象细化的模型检查的框架

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102257

T. Tóth, Á. Hajdu, András Vörös, Zoltán Micskei, I. Majzik

引用次数: 34

Solving linear arithmetic with SAT-based model checking 基于sat的模型检验求解线性算法

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102240

Y. Vizel, Alexander Nadel, S. Malik

{"title":"Solving linear arithmetic with SAT-based model checking","authors":"Y. Vizel, Alexander Nadel, S. Malik","doi":"10.23919/FMCAD.2017.8102240","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102240","url":null,"abstract":"We present LIAMC, a novel decision procedure for (quantifier-free) linear arithmetic over both integers modulo 2N (LIAn) and integers (LIA). There is no need to explain our motivation to design a new efficient decision procedure for the widely used LIA logic. A LIAn decision procedure can be extremely useful in the context of software (SW) verification. SW verification usually requires to reason about arithmetic constraints over finite integers. To that end, modern SW verification tools commonly use fixed-width bit-vector (BV) solvers. However, BV solvers' efficiency drops dramatically as the width increases. To solve the performance problem, LIA solvers are applied, but they are imprecise as they cannot handle integer overflow. An efficient LIAN solver would be the ideal solution in this context. Our decision procedure LIAMC is based on a transformation of linear arithmetic into safety verification. We treat integers as unbounded streams of bits over time. More precisely, for each input integer, the least significant bit (LSB) corresponds to time 0 in the corresponding stream, and the k-th bit corresponds to the bit received at time k. LIAMC then uses SAT-based model checking (SATMC) to solve the resulting problem. In order to achieve efficiency, LIAMC uses two forms of generalization. First, if it finds a formula to be unsatisfiable for width N, it tries to generalize this result for all the widths. Second, if LIAMC finds a formula to be satisfiable for width N, it tries to “extend” and thus generalize the assignment to a wider target width. To evaluate LIAMC we used the QF_LIA subset of SMT-COMP'16, and ran two sets of experiments. First, we reinterpreted the QF_LIA over fixed-width bit-vectors of varying widths and compared LIAMC in LIAn mode to both Boolector and Z3. LIAMC solved the most satisfiable instances out of the three even for the shortest width 32. Second, we compared LIAMC to CVC4 and Z3 on the original QF_LIA benchmarks. LIAMC was able to solve many instances that had not been solved by the other solvers.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116701720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Modular SMT-based analysis of nonlinear hybrid systems 基于模块化smt的非线性混合系统分析

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102258

K. Bae, Sicun Gao

引用次数: 8

Learning to prove safety over parameterised concurrent systems 学习证明参数化并发系统的安全性

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-09-21 DOI: 10.23919/FMCAD.2017.8102244

Yu-Fang Chen, Chih-Duo Hong, A. Lin, Philipp Rümmer

{"title":"Learning to prove safety over parameterised concurrent systems","authors":"Yu-Fang Chen, Chih-Duo Hong, A. Lin, Philipp Rümmer","doi":"10.23919/FMCAD.2017.8102244","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102244","url":null,"abstract":"We revisit the classic problem of proving safety over parameterised concurrent systems, i.e., an infinite family of finite-state concurrent systems that are represented by some finite (symbolic) means. An example of such an infinite family is a dining philosopher protocol with any number n of processes (n being the parameter that defines the infinite family). Regular model checking is a well-known generic framework for modelling parameterised concurrent systems, where an infinite set of configurations (resp. transitions) is represented by a regular set (resp. regular transducer). Although verifying safety properties in the regular model checking framework is undecidable in general, many sophisticated semi-algorithms have been developed in the past fifteen years that can successfully prove safety in many practical instances. In this paper, we propose a simple solution to synthesise regular inductive invariants that makes use of Angluin's classic L∗ algorithm (and its variants). We provide a termination guarantee when the set of configurations reachable from a given set of initial configurations is regular. We have tested L∗ algorithm on standard (as well as new) examples in regular model checking including the dining philosopher protocol, the dining cryptographer protocol, and several mutual exclusion protocols (e.g. Bakery, Burns, Szymanski, and German). Our experiments show that, despite the simplicity of our solution, it can perform at least as well as existing semi-algorithms.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128355774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Safety verification of phaser programs 相位器程序的安全验证

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-08-09 DOI: 10.23919/FMCAD.2017.8102243

Zeinab Ganjei, Ahmed Rezine, P. Eles, Zebo Peng

{"title":"Safety verification of phaser programs","authors":"Zeinab Ganjei, Ahmed Rezine, P. Eles, Zebo Peng","doi":"10.23919/FMCAD.2017.8102243","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102243","url":null,"abstract":"We address the problem of statically checking control state reachability (as in possibility of assertion violations, race conditions or runtime errors) and plain reachability (as in deadlock-freedom) of phaser programs. Phasers are a modern non-trivial synchronization construct that supports dynamic parallelism with runtime registration and deregistration of spawned tasks. They allow for collective and point-to-point synchronizations. For instance, phasers can enforce barriers or producer-consumer synchronization schemes among all or subsets of the running tasks. Implementations are found in modern languages such as Habanero Java. Phasers essentially associate phases to individual tasks and use their runtime values to restrict possible concurrent executions. Unbounded phases may result in infinite transition systems even in the case of programs only creating finite numbers of tasks and phasers. We introduce an exact gap-order based procedure that always terminates when checking control reachability for programs generating bounded numbers of coexisting tasks and phasers. We also show verifying plain reachability is undecidable even for programs generating few tasks and phasers. We then explain how to turn our procedure into a sound analysis for checking plain reachability (including deadlock freedom). We report on preliminary experiments with our open source tool.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133672922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Automatic verification of application-tailored OSEK kernels 自动验证应用程序定制的OSEK内核

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-08-08 DOI: 10.23919/FMCAD.2017.8102260

Hans-Peter Deifel, Merlin Göttlinger, Stefan Milius, Lutz Schröder, Christian J. Dietrich, D. Lohmann

{"title":"Automatic verification of application-tailored OSEK kernels","authors":"Hans-Peter Deifel, Merlin Göttlinger, Stefan Milius, Lutz Schröder, Christian J. Dietrich, D. Lohmann","doi":"10.23919/FMCAD.2017.8102260","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102260","url":null,"abstract":"The OSEK industrial standard governs the design of embedded real-time operating systems in the automotive domain. We report on efforts to develop verification methods for OSEK-conformant compilers, specifically of a code generator that weaves system calls and application code using a static configuration file, producing a stand-alone application that incorporates the relevant parts of the kernel. Our methodology involves two verification steps: On the one hand, we extract an OS-application interaction graph during the compilation phase and verify that it conforms to the standard, in particular regarding prioritized scheduling and interrupt handling. To this end, we generate from the configuration file a temporal specification of standard-conformant behaviour and model check the arising formulas on a labelled transition system extracted from the interaction graph. On the other hand, we verify that the actual generated code conforms to the interaction graph; this is done by graph isomorphism checking of the interaction graph against a dynamically-explored state-transition graph of the generated system.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125483289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6