2017 Formal Methods in Computer Aided Design (FMCAD)最新文献

Lasso detection using partial-state caching 使用部分状态缓存的套索检测

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-02 DOI: 10.23919/FMCAD.2017.8102245

Rashmi Mudduluru, Pantazis Deligiannis, Ankush Desai, A. Lal, S. Qadeer

{"title":"Lasso detection using partial-state caching","authors":"Rashmi Mudduluru, Pantazis Deligiannis, Ankush Desai, A. Lal, S. Qadeer","doi":"10.23919/FMCAD.2017.8102245","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102245","url":null,"abstract":"We study the problem of finding liveness violations in real-world asynchronous and distributed systems. Unlike a safety property, which asserts that certain bad states should never occur during execution, a liveness property states that a program should not remain in a bad state for an infinitely long period of time. Checking for liveness violations is essential to ensure that a system will always make progress in production. The violation of a liveness property can be demonstrated by a finite execution where the same system state repeats twice (known as lasso). However, this requires the ability to capture the state precisely, which is arguably impossible in real-world systems. For this reason, previous approaches have instead relied on demonstrating a long execution where the system remains in a bad state. However, this hampers debugging because the produced trace can be very long, making it hard to understand. Our work aims to find liveness violations in real-world systems while still producing lassos as a bug witness. Our technique relies only on partially caching the system state, which is feasible to achieve efficiently in practice. To make up for imprecision in caching, we use retries: a potential lasso, where the same partial state repeats twice, is replayed multiple times to gain certainty that the execution is indeed stuck in a bad state. We have implemented our technique in the P# programming language and evaluated it on real production systems and several challenging academic benchmarks.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"1 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Efficient generation of all minimal inductive validity cores 有效地生成所有最小的归纳有效性核心

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-02 DOI: 10.23919/FMCAD.2017.8102238

Elaheh Ghassabani, M. Whalen, Andrew Gacek

{"title":"Efficient generation of all minimal inductive validity cores","authors":"Elaheh Ghassabani, M. Whalen, Andrew Gacek","doi":"10.23919/FMCAD.2017.8102238","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102238","url":null,"abstract":"Symbolic model checkers can construct proofs of safety properties over complex models, but when a proof succeeds, the results do not generally provide much insight to the user. Recently, proof cores (alternately, for inductive model checkers, Inductive Validity Cores (IVCs)) were introduced to trace a property to a minimal set of model elements necessary for proof. Minimal IVCs facilitate several engineering tasks, including performing traceability and analyzing requirements completeness, that usually rely on the minimality of IVCs. However, existing algorithms for generating an IVC are either expensive or only able to find an approximately minimal IVC. Besides minimality, computing all minimal IVCs of a given property is an interesting problem that provides several useful analyses, including regression analysis for testing/proof, determination of the minimum (as opposed to minimal) number of model elements necessary for proof, the diversity examination of model elements leading to proof, and analyzing fault tolerance. This paper proposes an efficient method for finding all minimal IVCs of a given property proving its correctness and completeness. We benchmark our algorithm against existing IVC-generating algorithms and show, in many cases, the cost of finding all minimal IVCs by our technique is similar to finding a single minimal IVC using existing algorithms.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123223015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Hardware model checking competition 2017 2017硬件模型检测大赛

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-02 DOI: 10.23919/FMCAD.2017.8102233

Armin Biere, T. V. Dijk, Keijo Heljanko

引用次数: 33

The FMCAD 2017 graduate student forum FMCAD 2017研究生论坛

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-02 DOI: 10.23919/FMCAD.2017.8102234

Keijo Heljanko

引用次数: 4

How formal analysis and verification add security to blockchain-based systems 形式化分析和验证如何为基于区块链的系统增加安全性

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-02 DOI: 10.23919/FMCAD.2017.8102228

Shin'ichiro Matsuo

引用次数: 18

ZSstrS: A string solver with theory-aware heuristics ZSstrS:一个具有理论感知启发式的字符串求解器

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102241

Murphy Berzish, Vijay Ganesh, Yunhui Zheng

引用次数: 80

Automated formal reasoning about AWS systems 关于AWS系统的自动形式推理

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102231

B. Cook

引用次数: 1

Property directed reachability with word-level abstraction 具有字级抽象的属性定向可达性

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102251

Yen-Sheng Ho, A. Mishchenko, R. Brayton

引用次数: 14

SMT-based analysis of switching multi-domain linear Kirchhoff networks 基于smt的切换多域线性Kirchhoff网络分析

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102259

A. Cimatti, Sergio Mover, Mirko Sessa

{"title":"SMT-based analysis of switching multi-domain linear Kirchhoff networks","authors":"A. Cimatti, Sergio Mover, Mirko Sessa","doi":"10.23919/FMCAD.2017.8102259","DOIUrl":"https://doi.org/10.23919/FMCAD.2017.8102259","url":null,"abstract":"Many critical systems are based on the combination of components from different physical domains (e.g. mechanical, electrical, hydraulic), and are mathematically modeled as Switched Multi-Domain Linear Kirchhoff Networks (Smdlkn). In this paper, we tackle a major obstacle to formal verification of Smdlkn, namely devising a global model amenable to verification in the form of a Hybrid Automaton. This requires the combination of the local dynamics of the components, expressed as Differential Algebraic Equations, according to Kirchhoff's laws, depending on the (exponentially many) operation modes of the network. We propose an automated SMT-based method to analyze networks from multiple physical domains, detecting which modes induce invalid (i.e. inconsistent) constraints, and to produce a Hybrid Automaton model that accurately describes, in terms of Ordinary Differential Equations, the system evolution in the valid modes, catching also the possible non-deterministic behaviors. The experimental evaluation demonstrates that the proposed approach allows several complex multi-domain systems to be formally analyzed and model checked against various system requirements.","PeriodicalId":405292,"journal":{"name":"2017 Formal Methods in Computer Aided Design (FMCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130855114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Tagged BDDs: Combining reduction rules from different decision diagram types 标记bdd:结合来自不同决策图类型的约简规则

2017 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2017-10-01 DOI: 10.23919/FMCAD.2017.8102248

T. V. Dijk, R. Wille, R. Meolic

引用次数: 18