2012 25th International Conference on VLSI Design最新文献_第8页

Tutorial T8B: Wireless System Design and Systems Engineering Challenges 教程T8B:无线系统设计和系统工程挑战

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.37

Kameswara Rao, M. B. Reddy, Ravi Kishore

引用次数: 0

Power Aware Post-Manufacture Tuning of MIMO Receiver Systems MIMO接收机系统的功率感知制造后调谐

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.61

D. Banerjee, Shreyas Sen, S. Devarakond, A. Chatterjee

{"title":"Power Aware Post-Manufacture Tuning of MIMO Receiver Systems","authors":"D. Banerjee, Shreyas Sen, S. Devarakond, A. Chatterjee","doi":"10.1109/VLSID.2012.61","DOIUrl":"https://doi.org/10.1109/VLSID.2012.61","url":null,"abstract":"This paper presents a methodology for post-manufacture tuning of MIMO (Multiple-Input-Multiple-Output) wireless systems aimed at increasing device manufacturing yield under large process variations. The goal is to achieve specified system-level EVM (Error Vector Magnitude) targets for MIMO receiver systems by tuning the individual MIMO receiver subsystems whose combined gain, noise and nonlinearity parameters determine the overall system-level EVM metric. While there has been prior work on tuning of SISO systems, the current work is novel due to the fact that the performances of individual receiver subsystems can combine in different ways to result in the same system-level EVM value. As the systems are tuned to meet the system level end-to-end metric it is ensured that all devices that are tuned for EVM consume the least amount of power possible. Tuning infrastructure for MIMO receivers and underlying tuning algorithms are developed in this work. A 1×2 MIMO system for a 2.4 GHz OFDM WLAN is used to demonstrate the core ideas of this research. This work demonstrates a 23% increase in yield of the device with an average power increase of 9.18% for the system under consideration.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121771659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS Extensions 教程T1:使用SystemC AMS扩展设计混合信号系统

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.28

Sumit Adhikari, Markus Damm, C. Grimm, F. Pêcheux

引用次数: 0

Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design 第4课:片上系统设计中的知识产权保护与安全

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.31

S. Sur-Kolay, S. Bhunia

{"title":"Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design","authors":"S. Sur-Kolay, S. Bhunia","doi":"10.1109/VLSID.2012.31","DOIUrl":"https://doi.org/10.1109/VLSID.2012.31","url":null,"abstract":"Gigascale integration in recent semiconductor technology mandates design reuse in order to meet the design specifications in time. Electronic description of VLSI design being an intellectual property (IP), may be infringed upon during design reuse. This calls for incorporating techniques for intellectual property protection in the VLSI design flow. The IP of VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs because in addition to its physical and structural description, it has also a behavioral specification which should remain unaltered after application of IP protection techniques. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security. This tutorial aims at presenting the major concerns related to IP security that are significant to both the circuit designers and developers of CAD tools. The nature of threats are broadly categorized as (i) misappropriation by hacking during electronic commerce and intentional reselling mostly at design level, and (ii) unauthorized design retrieval. Various attack models and the mechanisms for effective counter measures such as encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspect, specific to chip designs, will be discussed. First, the scenario of digital rights management, attack models and security goals will be described. Next, the existing approaches for protection of soft IPs such as HDL codes, firm IPs especially at the value-added layout level, and hard IPs including DFM-enhanced layout will be presented. This will include a number of published research results by the presenters. Finally, the recent advances in tackling security issues for design of smart cards and crypto processors will be surveyed.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132929269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model 基于HiSIM-HV紧凑模型的部分耗尽SOI演示场效应管子电路建模

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.105

T. Agarwal, M. J. Kumar

引用次数: 0

Synthesis of Reversible Circuits Using Heuristic Search Method 基于启发式搜索法的可逆电路综合

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.92

K. Datta, G. Rathi, I. Sengupta, H. Rahaman

引用次数: 22

Eliminating Performance Penalty of Scan 消除扫描的性能损失

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.95

O. Sinanoglu

引用次数: 6

A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC 55mw 300MS/s 8位CMOS并行流水线ADC

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.44

M. K. Hati, T. K. Bhattacharyya

引用次数: 5

Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory 宽度感知的细粒度动态供应门控:一种低功耗数据路径和存储器的设计方法

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.94

L. Wang, Somnath Paul, S. Bhunia

{"title":"Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory","authors":"L. Wang, Somnath Paul, S. Bhunia","doi":"10.1109/VLSID.2012.94","DOIUrl":"https://doi.org/10.1109/VLSID.2012.94","url":null,"abstract":"With increasing contribution of leakage in total active power, run-time leakage control techniques are becoming extremely important. Supply gating provides an effective, low-overhead and technology scalable approach for active leakage reduction through the well-known \"stacking effect\". However, conventional supply gating approaches are typically coarse-grained in both space and time - i.e. are applied to large data path or memory blocks when an entire logic/memory block is idle for sufficiently long period. They suffer from limited applicability at run time. On the other hand, fine-grained supply gating is constrained primarily by the large wake-up delay and wake-up power overhead. In this paper, we propose a novel fine-grained width-aware dynamic supply gating (WADSG) approach to reduce both active leakage and redundant switching power in data path and embedded memory (e.g. L1/L2 cache). The approach exploits the abundance of narrow-width (NW) operands in general-purpose and embedded applications to \"supply-gate\" unused parts of integer execution units and memory blocks while they are in use. We introduce a novel levelized gating strategy to virtually eliminate the wake-up delay overhead. We employ the proposed WADSG approach to a super scalar processor. To reduce the wake-up power we use a width aware instruction issue policy. In case of L1 and L2 cache, we store the width information per \"ways\" of associative cache and supply-gate the most significant bits of the NW ways. We also propose a width-aware block allocation and replacement policy to maximize the number of NW ways. Simulation results for 45nm technology with Spec2k benchmarks show major savings (34.5%) in total processor power (considering both switching and active leakage power) with no performance impact. As a by-product, the proposed scheme also improves the thermal profile of both data path and memory.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126460497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Embedded Tutorial ET4: Advanced Techniques for Programming Networked Embedded Systems 嵌入式教程ET4:网络嵌入式系统编程的高级技术

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.39

V. Raghunathan

引用次数: 0