2012 25th International Conference on VLSI Design最新文献_第7页

Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate 基于本体偏置的泄漏功率降低对软错误率的影响

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.49

Warin Sootkaneung, K. Saluja

引用次数: 3

Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters GBPS速率发射机的自致供电降噪技术

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.52

Nitin Gupta, Tapas Nandy, P. Bala

引用次数: 4

A Rapid Methodology for Multi-mode Communication Circuit Generation 多模通信电路的快速生成方法

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.71

L. Tang, Jorgen Peddersen, S. Parameswaran

{"title":"A Rapid Methodology for Multi-mode Communication Circuit Generation","authors":"L. Tang, Jorgen Peddersen, S. Parameswaran","doi":"10.1109/VLSID.2012.71","DOIUrl":"https://doi.org/10.1109/VLSID.2012.71","url":null,"abstract":"The need to integrate multiple wireless communication protocols into a single low-cost, low power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents an efficient methodology for integrating multiple wireless protocols in an ASIC which minimizes resource occupation. A hierarchical data path merging algorithm is developed to find common shareable components in two different communication circuits. The data path merging approach will build a combined generic circuit with inserted multiplexers (MUXes) which can provide the same functionality of each individual circuit. The proposed method is orders of magnitude faster (well over 1000 times faster for realistic circuits) than the existing data path merging algorithm (with an overhead of 3% additional area) and can switch communication protocols on the fly (i.e. it can switch between protocols in a single clock cycle), which is a desirable feature for seemingly simultaneous multi-mode wireless communication. Wireless LAN (WLAN) 802.11a, WLAN802.11b and Ultra Wide Band (UWB) transmission circuits are merged to prove the efficacy of our proposal.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122058167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques 伽罗瓦域乘法器的计算机代数形式化验证

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.102

Jinpeng Lv, P. Kalla

引用次数: 12

Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM 光晕植入阴影和掩膜层边缘后向散射对65nm SRAM器件漏电流的影响

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.106

H. C. Srinivasaiah

{"title":"Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM","authors":"H. C. Srinivasaiah","doi":"10.1109/VLSID.2012.106","DOIUrl":"https://doi.org/10.1109/VLSID.2012.106","url":null,"abstract":"Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Real-Time, Content Aware Camera -- Algorithm -- Hardware Co-Adaptation for Minimal Power Video Encoding 实时，内容感知摄像机-算法-硬件协同适应最小功耗视频编码

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.78

J. W. Wells, Jayaram Natarajan, A. Chatterjee, I. Barlas

引用次数: 4

At-speed Testing of Asynchronous Reset De-assertion Faults 异步复位反断言故障的快速测试

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.97

A. Jain, Maheedhar Jalasutram, S. Vooka, Prasun Nair, Neeraj Pradhan

{"title":"At-speed Testing of Asynchronous Reset De-assertion Faults","authors":"A. Jain, Maheedhar Jalasutram, S. Vooka, Prasun Nair, Neeraj Pradhan","doi":"10.1109/VLSID.2012.97","DOIUrl":"https://doi.org/10.1109/VLSID.2012.97","url":null,"abstract":"In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger 带差分微带天线和片上充电器的集成CMOS射频能量采集器

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.72

Mahima Arrawatia, Varish Diddi, H. Kochar, M. Baghini, G. Kumar

{"title":"An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger","authors":"Mahima Arrawatia, Varish Diddi, H. Kochar, M. Baghini, G. Kumar","doi":"10.1109/VLSID.2012.72","DOIUrl":"https://doi.org/10.1109/VLSID.2012.72","url":null,"abstract":"This paper presents an energy harvesting system which extracts energy from radio frequency radiation for battery charging applications. It comprises of a new differential center tapped Micro strip antenna, off-chip matching circuit, on-chip novel CMOS rectifier and control circuitry in 180nm CMOS technology. For on-chip modules, thick oxide devices have been used so as to meet the charging requirements of the target batteries. The designed battery charging module charges either of 250 Ah and 10 Ah batteries according to the selected battery and available input power. The 250 Ah battery is charged at input power of 2dBm and 10 Ah battery is charged at input power of -6.5dBm. The fabricated antenna has a gain of 8.3dB and a VSWR less than 2 in the bandwidth from 844 to 970MHz. An efficient Periodic Steady State(PSS)-based power matching technique is also presented which improves the system efficiency. For 0dBm input power at 950 MHz to the antenna the proposed technique leads to 55.2% efficiency of RF to DC converter system. In addition to the integrated design a discrete rectifier using high frequency Schottky diodes and differential micro strip antenna at the input are fabricated. The discrete system uses the proposed matching technique and exhibits efficiency of 40% for-11dBm received power by the antenna.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125092938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Set-Cover Heuristics for Two-Level Logic Minimization 两级逻辑最小化的集盖启发式

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.70

Ankit Kagliwal, S. Balachandran

引用次数: 6

A Fast Equation Free Iterative Approach to Analog Circuit Sizing 模拟电路尺寸的快速无方程迭代方法

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.99

S. Maji, P. Mandal

引用次数: 5