A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC

Abstract

This paper describes 8-bit 300MS/s 7-stages parallel pipeline ADC with 1.5-bit per stage and power efficient architecture is designed by sharing an amplifier between two pipeline stages, introducing the proper clock timing between the two parallel stages. This architecture is realized by eight no. of amplifier and the sample hold architecture is designed by using double sampling sample hold (DSSH) technique. A wide swing and wide bandwidth regulated folded cascode and power efficient dynamic comparator has been developed to further reduce the power consumption of the pipeline ADC. The ADC is implemented in 0.18 μm CMOS process technology, achieves 57.40 dB spurious free dynamic range (SFDR), 49.078 dB signal to noise distortion ratio (SNDR), 7.86 effective no of bit (ENOB) and consumes 55 mW from 1.8 V supply. The resulting figure of merit (FOM) is 0.789 PJ/conversion step.