2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第4页

Hardware implementation of a medium access control layer for industrial wireless LAN 工业无线局域网介质访问控制层的硬件实现

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482465

K. Tittelbach-Helmrich, Z. Stamenkovic

引用次数: 3

Real-time sleep detection and warning system to ensure driver's safety based on EEG 基于脑电图的驾驶员睡眠实时检测预警系统

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482475

Michael S. Saleab, Mohamed A. Abd El-Ghany, Ramez M. Toma, K. Hofmann

引用次数: 5

Test of automotive embedded processors with high diagnostic resolution 具有高诊断分辨率的汽车嵌入式处理器测试

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482443

Christian Gleichner, H. Vierhaus

引用次数: 0

High-level modeling and testing of multiple control faults in digital systems 数字系统中多控制故障的高级建模与测试

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482445

Artjom Jasnetski, S. Oyeniran, A. Tsertov, Mario Schölzel, R. Ubar

{"title":"High-level modeling and testing of multiple control faults in digital systems","authors":"Artjom Jasnetski, S. Oyeniran, A. Tsertov, Mario Schölzel, R. Ubar","doi":"10.1109/DDECS.2016.7482445","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482445","url":null,"abstract":"A new method for high level fault modeling to improve the test generation for the control parts of digital systems was proposed. We developed a new high-level functional fault model based on High-Level Decision Diagrams (HLDD). It allows uniform handling of possible defects in different control functions related to instruction decoding, data addressing, and data manipulation. It was shown how the proposed high-level fault model can be mapped on the low-level faults of a joint class of stuck-at faults (SAF), conditional SAF and bridging faults. We proposed uniform procedures for high-level fault activation as a graph traversing procedure on HLDDs related to selection of control signals, and for fault propagation as a task of solving data constraints without using implementation details. Experimental results demonstrated that combining both, high-level control fault reasoning and low-level test generation for data part of a system can help to achieve higher fault coverage and detection of redundant faults than using low-level test generation approach alone.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133021680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A mixed domain sizing approach for RF circuit synthesis 射频电路合成的混合域尺寸方法

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482437

Engin Afacan, Günhan Dündar

引用次数: 18

Comparative BTI analysis for various sense amplifier designs 各种感测放大器设计的比较BTI分析

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482438

I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, P. Raghavan, F. Catthoor

{"title":"Comparative BTI analysis for various sense amplifier designs","authors":"I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, P. Raghavan, F. Catthoor","doi":"10.1109/DDECS.2016.7482438","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482438","url":null,"abstract":"With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). This paper presents a comparative study of the BTI impact while considering varying supply voltages and temperatures for three memory sense amplifier (SA) designs: low power (LP), mid power/performance (MP), and high performance (HP). As an evaluation metric, the sensing delay (SD) of the three designs is analyzed for various workloads using 45nm technology. The results show that HP SA degrades faster than MP SA and LP SA irrespective of the workload, supply voltage, and temperature. At nominal supply voltage and temperature, HP degrades up to 1.62x faster than MP, and up to 1.94x faster than LP designs for the worst case workload. In addition, the results show that an increase of 10% in power supply has a marginal impact on the relative degradation. In contrast, the results show that a temperature increment significantly worsens the BTI impact. Finally, the results show that for 16nm technology, BTI impact becomes worse and even causes read failures. This clearly indicates that designing for reliability is not only strongly application dependent, but also technology node dependent. Hence, one has to carefully consider the targeted application, design, and technology node in order to provide appropriate solutions.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132432216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

BioSoC: Highly integrated System-on-Chip for health monitoring BioSoC:高度集成的健康监测系统芯片

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482464

Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, T. Borejko, Aleh Halauko, A. Jarosz, Jakub Kopanski, E. Kurjata-Pfitzner, Paweł Narczyk, Maciej Plasota, A. Wielgus, W. Pleskacz

{"title":"BioSoC: Highly integrated System-on-Chip for health monitoring","authors":"Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, T. Borejko, Aleh Halauko, A. Jarosz, Jakub Kopanski, E. Kurjata-Pfitzner, Paweł Narczyk, Maciej Plasota, A. Wielgus, W. Pleskacz","doi":"10.1109/DDECS.2016.7482464","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482464","url":null,"abstract":"The BioSoC is a highly integrated SoC that consists of analog front-ends, analog to digital converters and a 32-bit microcontroller - Adelite. The designed IC allows for dynamic acquisition and processing of the most important human physiological parameters. The provided analog interfaces to external electrodes and sensors allow measurement of electrocardiograms (ECG), electromyograms (EMG), skin temperature and resistance, and respiration rate (RR). After analog processing signals are sampled and digitized in analog-to-digital converters they can be further processed in a 32-bit microcontroller Adelite. The clock frequency of the microprocessor core is configurable from 32 kHz up to 16 MHz. The microcontroller is equipped with many digital interfaces and peripherals, such as 2×UART and 2×SPI with DMA channels, 16 GPIOs and 5 timers along with RTC. The BioSoC makes it possible to build highly integrated devices with rich functionalities in the area of telemedicine that respond to the growing demand for portable health monitoring. The BioSoC was designed and fabricated in UMC CMOS 130 nm technology process and occupies the area of 25mm2.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Introduction to approximate computing: Embedded tutorial 近似计算导论:嵌入式教程

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482460

L. Sekanina

引用次数: 15

FPGA-controlled PCBA power-on self-test using processor's debug features fpga控制的PCBA上电自检，利用处理器的调试功能

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482458

B. Du, E. Sánchez, M. Reorda, J. P. Acle, A. Tsertov

{"title":"FPGA-controlled PCBA power-on self-test using processor's debug features","authors":"B. Du, E. Sánchez, M. Reorda, J. P. Acle, A. Tsertov","doi":"10.1109/DDECS.2016.7482458","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482458","url":null,"abstract":"When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133326741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Early-stage verification of power-management specification in low-power systems design 低功耗系统设计中电源管理规范的早期验证

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI: 10.1109/DDECS.2016.7482449

Dominik Macko, K. Jelemenská, P. Cicák

引用次数: 6