2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)最新文献_第6页

Evaluation of Blue Gene/Q hardware support for transactional memories 评估Blue Gene/Q硬件对事务性存储器的支持

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370836

Amy Wang, Matthew Gaudet, Peng Wu, J. N. Amaral, M. Ohmacht, Christopher Barton, Raúl Silvera, Maged M. Michael

引用次数: 220

PGCapping: Exploiting power gating for power capping and core lifetime balancing in CMPs PGCapping:在cmp中利用功率门控实现功率封顶和核心寿命平衡

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370821

Kai Ma, Xiaorui Wang

{"title":"PGCapping: Exploiting power gating for power capping and core lifetime balancing in CMPs","authors":"Kai Ma, Xiaorui Wang","doi":"10.1145/2370816.2370821","DOIUrl":"https://doi.org/10.1145/2370816.2370821","url":null,"abstract":"Optimizing the performance of a chip multiprocessor (CMP) within a power cap has recently received a lot of attention. However, most existing solutions rely solely on DVFS, which is anticipated to have only limited actuation ranges in the future. Power gating shuts down idling cores in a CMP, such that more power can be shifted to the cores that run applications for better CMP performance. However, current preliminary studies on integrating the two knobs focus on deciding the power gating and DVFS levels in a tightly coupled fashion, with much less attention given to the direction of decoupled designs. By decoupling the two knobs that may interfere with each other, individual knob management algorithms can be less complex and more efficient to take advantage of the characteristics of different knobs. This paper proposes PGCapping, a decoupled design to integrate power gating with DVFS for CMP power capping. To fully utilize the power headroom that is reserved through power gating, PGCapping enables per-core overclocking on turned-on cores that run sequential applications. However, per-core overclocking may make some cores age much faster than others and thus become the reliability bottleneck in the whole system. Therefore, PGCapping also uses power gating to balance the core lifetimes. Our empirical results on a hardware testbed show that the proposed scheme achieves up to 42.0% better average application performance than five state-of-the-art power capping baselines for realistic multi-core applications, i.e., a mixed group of PARSEC and SPEC CPU2006 benchmarks. Furthermore, our extensive simulation results with real-world traces demonstrate that a lightweight lifetime balancing algorithm (based on power gating) can increase the CMP lifetime by 9.2% on average.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 78

XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems XPoint缓存:为2D和3D多核系统扩展现有的基于总线的一致性协议

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370829

R. Dreslinski, Thomas Manville, Korey Sewell, R. Das, N. Pinckney, Sudhir K. Satpathy, D. Blaauw, D. Sylvester, T. Mudge

{"title":"XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems","authors":"R. Dreslinski, Thomas Manville, Korey Sewell, R. Das, N. Pinckney, Sudhir K. Satpathy, D. Blaauw, D. Sylvester, T. Mudge","doi":"10.1145/2370816.2370829","DOIUrl":"https://doi.org/10.1145/2370816.2370829","url":null,"abstract":"With multi-core processors now mainstream, the shift to many-core processors poses a new set of design challenges. In particular, the scalability of coherence protocols remains a significant challenge. While complex Network-on-Chip interconnect fabrics have been proposed and in some cases implemented, most of industry has slowly evolved existing coherence solutions to meet the needs of a growing number of cores. Industries' slow adoption of Network-on-Chip designs is in large part due to the significant effort needed to design and verify the system. However, simply scaling bus-based coherence is not straightforward either because of increased contention and latency on the bus for large core counts. This paper proposes a new architecture, XPoint, which does not need to modify existing bus-based snooping coherence protocols to scale to 64 core systems. XPoint employs interleaved cache structures with detailed floorplaning and system analysis to reduce contention at high core counts. Results show that the XPoint system achieves, on average, a 28× and 35× speedup over a single core design on the Splash2 benchmarks for a 32 and 64 core system respectively (a 1.6× improvement over a 64 core conventional bus). XPoint is also evaluated as a 3D stacked system to reduce further bus latency. Results show a 29× and 45× speedup for 32 and 64 core systems respectively (a 2.1× improvement over a 64 core conventional bus and within 8% of the speedup of a 64 core system with an ideal interconnect). Measurements also show that the XPoint system decreases bus contention of a 64 core system to only 13% higher than that of an 8-core design (a 29× improvement over a 64 core conventional bus).","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126003132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

SkipCache: Miss-rate aware cache management SkipCache:丢失率感知缓存管理

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370907

K. Raghavendra, Tripti S. Warrier, M. Mutyam

引用次数: 4

Auto-parallelizing stateful distributed streaming applications 自动并行化有状态分布式流应用程序

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370826

S. Schneider, Martin Hirzel, B. Gedik, Kun-Lung Wu

{"title":"Auto-parallelizing stateful distributed streaming applications","authors":"S. Schneider, Martin Hirzel, B. Gedik, Kun-Lung Wu","doi":"10.1145/2370816.2370826","DOIUrl":"https://doi.org/10.1145/2370816.2370826","url":null,"abstract":"Streaming applications transform possibly infinite streams of data and often have both high throughput and low latency requirements. They are comprised of operator graphs that produce and consume data tuples. The streaming programming model naturally exposes task and pipeline parallelism, enabling it to exploit parallel systems of all kinds, including large clusters. However, it does not naturally expose data parallelism, which must instead be extracted from streaming applications. This paper presents a compiler and runtime system that automatically extract data parallelism for distributed stream processing. Our approach guarantees safety, even in the presence of stateful, selective, and user-defined operators. When constructing parallel regions, the compiler ensures safety by considering an operator's selectivity, state, partitioning, and dependencies on other operators in the graph. The distributed runtime system ensures that tuples always exit parallel regions in the same order they would without data parallelism, using the most efficient strategy as identified by the compiler. Our experiments using 100 cores across 14 machines show linear scalability for standard parallel regions, and near linear scalability when tuples are shuffled across parallel regions.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 81

The changing role of supercomputing 超级计算不断变化的角色

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370818

Peter J. Ungaro

引用次数: 0

High-performance analysis of filtered semantic graphs 过滤语义图的高性能分析

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370897

A. Buluç, A. Fox, J. Gilbert, S. Kamil, A. Lugowski, L. Oliker, Samuel Williams

{"title":"High-performance analysis of filtered semantic graphs","authors":"A. Buluç, A. Fox, J. Gilbert, S. Kamil, A. Lugowski, L. Oliker, Samuel Williams","doi":"10.1145/2370816.2370897","DOIUrl":"https://doi.org/10.1145/2370816.2370897","url":null,"abstract":"High performance is a crucial consideration when executing a complex analytic query on a massive semantic graph. In a semantic graph, vertices and edges carry “attributes” of various types. Analytic queries on semantic graphs typically depend on the values of these attributes; thus, the computation must either view the graph through a filter that passes only those individual vertices and edges of interest, or else must first materialize a subgraph or subgraphs consisting of only the vertices and edges of interest. The filtered approach is superior due to its generality, ease of use, and memory efficiency, but may carry a performance cost. In the Knowledge Discovery Toolbox (KDT), a Python library for parallel graph computations, the user writes filters in a high-level language, but those filters result in relatively low performance due to the bottleneck of having to call into the Python interpreter for each edge. In this work, we use the Selective Embedded JIT Specialization (SEJITS) approach to automatically translate filters defined by programmers into a lower-level efficiency language, bypassing the upcall into Python. We evaluate our approach by comparing it with the high-performance C++ /MPI Combinatorial BLAS engine, and show that the productivity gained by using a high-level filtering language comes without sacrificing performance.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134362484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

System-level power-performance efficiency modeling for emergent GPU architectures 新兴GPU架构的系统级功率性能效率建模

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370903

S. Song, K. Cameron

{"title":"System-level power-performance efficiency modeling for emergent GPU architectures","authors":"S. Song, K. Cameron","doi":"10.1145/2370816.2370903","DOIUrl":"https://doi.org/10.1145/2370816.2370903","url":null,"abstract":"System and application design choices have profound impact on energy efficiency. Consider the rise of GPUs in emergent supercomputer design. Massive parallelism and high throughput offer the potential for improving performance. However, for systems with multiple GPUs power usage can easily triple. Therefore, we need to quantitatively understand power, performance, and their interactive effects to determine when the increased power use of a GPU is warranted. In order to help application and system designers find power-performance bottlenecks and their causes, we need accurate models that balance abstraction and detail on emergent GPU architectures. The best available GPU power models are statisticalor simulation-based. Related statistical models use multiple linear regression (MLR) and hardware counter data to predict GPU power consumption in isolation. These models provide a good balance of abstraction and application/system detail but potentially ignore nonlinear relationships between power and performance. This could lead to inaccuracy for individual kernel power prediction. Related simulation models use emulated performance data combined with detailed architectural information to predict integrated GPU power-performance efficiency. These models provide enough detail to explore architectural design but ignore application/system level information and require architectural schematics and expertise. Furthermore, both statisticaland simulation-based models require significant adaptation to support modern complex GPU architectures with true cache hierarchies. Therefore, we propose separate system-level power and performance models of modern GPU based systems that can be integrated to better understand the relationships between power and performance at scale. Our runtime hardware counter driven approach combines an analytical performance model for GPU based systems with a machine-learning-based artificial neural network (ANN)","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125143585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Compiling to avoid communication 编译避免通信

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370840

K. Yelick

引用次数: 2

Integrating nanophotonics in GPU microarchitecture 纳米光子学在GPU微架构中的集成

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370878

Nilanjan Goswami, Zhongqi Li, A. Verma, Ramkumar Shankar, Tao Li

引用次数: 6