2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)最新文献_第7页

A low-overhead dynamic optimization framework for multicores 一个低开销的多核动态优化框架

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370899

Christopher W. Fletcher, R. Harding, O. Khan, S. Devadas

引用次数: 1

Optimizing datacenter power with memory system levers for guaranteed Quality-of-Service 利用内存系统杠杆优化数据中心电源，以保证服务质量

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370834

K. Sudan, S. Srinivasan, R. Balasubramonian, R. Iyer

引用次数: 14

HaLock: Hardware-assisted lock contention detection in multithreaded applications HaLock:多线程应用程序中硬件辅助的锁争用检测

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370854

Yongbing Huang, Zehan Cui, Licheng Chen, Wenli Zhang, Yungang Bao, Mingyu Chen

引用次数: 22

Runtime detection and optimization of collective communication patterns 集体通信模式的运行时检测和优化

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370856

T. Hoefler, Timo Schneider

{"title":"Runtime detection and optimization of collective communication patterns","authors":"T. Hoefler, Timo Schneider","doi":"10.1145/2370816.2370856","DOIUrl":"https://doi.org/10.1145/2370816.2370856","url":null,"abstract":"Parallelism is steadily growing, remote-data access will soon dominate the execution time of large-scale applications. Many large-scale communication patterns expose significant structure that can be used to schedule communications accordingly. In this work, we identify concurrent communication patterns and transform them to semantically equivalent but faster communications. We show a directed acyclic graph formulation for communication schedules and concisely define their synchronization and data movement semantics. Our dataflow solver computes an internal representation (IR) that is amenable to pattern detection. We demonstrate a detection algorithm for our IR that is guaranteed to detect communication kernels on subsets of the graph and replace the subgraph with hardware accelerated or hand-tuned kernels. Those techniques are implemented in an open-source detection and transformation framework to optimize communication patterns. Experiments show that our techniques can improve the performance of representative example codes by several orders of magnitude on two different systems. However, we also show that some collective detection problems on process subsets are NP-hard. The developed analysis techniques are a first important step towards automatic large-scale communication transformations. Our developed techniques open several avenues for additional transformation heuristics and analyses. We expect that such communication analyses and transformations will become as natural as pattern detection, just-in-time compiler optimizations, and autotuning are today for serial codes.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134016911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Transparent runtime deadlock elimination 透明的运行时死锁消除

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370905

Hari K. Pyla, S. Varadarajan

引用次数: 2

The evicted-address filter: A unified mechanism to address both cache pollution and thrashing 驱逐地址过滤器:解决缓存污染和抖动的统一机制

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370868

V. Seshadri, O. Mutlu, M. Kozuch, T. Mowry

引用次数: 126

Sandboxing transactional memory 沙箱事务内存

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370843

Luke Dalessandro, M. Scott

引用次数: 36

Scalability-based manycore partitioning 基于可伸缩性的多核分区

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370833

Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura

{"title":"Scalability-based manycore partitioning","authors":"Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura","doi":"10.1145/2370816.2370833","DOIUrl":"https://doi.org/10.1145/2370816.2370833","url":null,"abstract":"Multicore processors have been popular for years, and the industry is gradually shifting towards the era of manycore processors. Single-thread performance of microprocessors is not growing at a historical rate, but the existence of a number of active processes in the computer system and the continuing development of multi-threaded applications benefit from the growing core counts to sustain system throughput. This trend brings us a situation where a number of parallel applications simultaneously being executed on a single system. Since multi-threaded applications try to maximize its throughput by utilizing the whole system, each of them usually create equal or larger number of threads compared to underlying logical core counts. This introduces much greater number of threads to be co-scheduled in the entire system. However, each program has different characteristics (or scalability) and contends for shared resources, which are the CPU cores and memory hierarchies, with each other. Therefore, it is clear that OS thread scheduling will play a major role in achieving high system performance under such conditions. We develop a sophisticated scheduler that (1) dynamically predicts the scalability of programs via the use of hardware performance monitoring units, (2) decides the optimal number of cores to be allocated for each program, and (3) allocates the cores to programs while maximizing the system utilization to achieve fair and maximum performance. The evaluation results on a 48-core AMD Opteron system show improvements over the Linux scheduler for a variety of multiprogramming workloads.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131736569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Energy-efficient workload mapping in heterogeneous systems with multiple types of resources 具有多种类型资源的异构系统中的高效工作负载映射

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370912

Cong Liu

引用次数: 3

Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme 使用编译器辅助运行时一致性方案的gpu快速有效的自动内存管理

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370824

Sreepathi Pai, R. Govindarajan, M. J. Thazhuthaveetil

{"title":"Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme","authors":"Sreepathi Pai, R. Govindarajan, M. J. Thazhuthaveetil","doi":"10.1145/2370816.2370824","DOIUrl":"https://doi.org/10.1145/2370816.2370824","url":null,"abstract":"Exploiting the performance potential of GPUs requires managing the data transfers to and from them efficiently which is an error-prone and tedious task. In this paper, we develop a software coherence mechanism to fully automate all data transfers between the CPU and GPU without any assistance from the programmer. Our mechanism uses compiler analysis to identify potential stale accesses and uses a runtime to initiate transfers as necessary. This allows us to avoid redundant transfers that are exhibited by all other existing automatic memory management proposals. We integrate our automatic memory manager into the X10 compiler and runtime, and find that it not only results in smaller and simpler programs, but also eliminates redundant memory transfers. Tested on eight programs ported from the Rodinia benchmark suite it achieves (i) a 1.06× speedup over hand-tuned manual memory management, and (ii) a 1.29× speedup over another recently proposed compiler-runtime automatic memory management system. Compared to other existing runtime-only and compiler-only proposals, it also transfers 2.2× to 13.3× less data on average.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114921818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 50