2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)最新文献_第5页

Strategies based on green policies to the grid resource allocation 基于绿色策略的网格资源分配策略

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370910

Fábio Coutinho, L. A. V. Carvalho

引用次数: 2

TMNOC: A case of HTM and NoC Co-design for increased energy efficiency and concurrency TMNOC: HTM和NoC协同设计的一个案例，以提高能源效率和并发性

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370885

Lihang Zhao, Woojin Choi, J. Draper

{"title":"TMNOC: A case of HTM and NoC Co-design for increased energy efficiency and concurrency","authors":"Lihang Zhao, Woojin Choi, J. Draper","doi":"10.1145/2370816.2370885","DOIUrl":"https://doi.org/10.1145/2370816.2370885","url":null,"abstract":"Hardware Transactional Memory (HTM) designs must implement conflict detection to guarantee the correctness of transaction execution. A conflict occurs when more than one transaction access the same data and at least one of them attempts to modify the data. The corresponding conflict detection mechanism usually works at a cacheline level that fits naturally into the cache coherence protocol. Thus, the inter-transaction communication for conflict detection is usually mapped onto the coherence communication controlled by the directory-based coherence protocols. In this paper, we identify inefficiency introduced by such mappings. The net effect of such inefficiency is excessive on-chip network traffic that consumes substantial dynamic power as packets are switched over the routers and links. We present TMNOC, a HTM and Network-on-Chip (NoC) co-design to improve network energy efficiency. The on-chip network, instead of a passive communication substrate, proactively filters out transactional requests that waste energy yet having no contribution to the progress of transactions. Experiment results show that TMNOC reduces energy consumption of the on-chip network by 14.5% on average (up to 38%) across a wide range of transaction applications.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133145960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Visualizing transactional memory 可视化事务性内存

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370842

Justin Emile Gottschlich, M. Herlihy, Gilles A. Pokam, Jeremy G. Siek

引用次数: 19

Practically Private: Enabling high performance CMPs through compiler-assisted data classification 实际上私有:通过编译器辅助的数据分类启用高性能cmp

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370852

Yong Li, R. Melhem, A. Jones

{"title":"Practically Private: Enabling high performance CMPs through compiler-assisted data classification","authors":"Yong Li, R. Melhem, A. Jones","doi":"10.1145/2370816.2370852","DOIUrl":"https://doi.org/10.1145/2370816.2370852","url":null,"abstract":"State-of-the-art chip multiprocessor (CMP) proposals emphasize optimization to deliver computing power across many types of applications. Potentially significant performance improvements that leverage application specific characteristics such as data access behavior are missed by this approach. In this paper, we demonstrate that using fairly simple and inexpensive static analysis, data can be classified into private and shared. In addition, we develop a novel compiler-based approach to speculatively detect a third classification: practically private. We demonstrate that practically private data is ubiquitous in parallel applications and leveraging this classification provides opportunities to benefit performance. While this proposed data classification scheme can be applied to many micro-architectural constructs including the TLB, coherence directory and interconnect, we demonstrate its potential through an efficient cache coherence design. Specifically, we show that the compiler-assisted mechanism reduces an average of 46% coherence traffic and achieves up to 13%, 9%, and 5% performance improvement over shared, private, and state-of-the-art NUCA-based caching, respectively depending on scenarios.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Fine-grained parallel traversals of irregular data structures 不规则数据结构的细粒度并行遍历

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370896

Bin Ren, G. Agrawal, J. Larus, Todd Mytkowicz, T. Poutanen, Wolfram Schulte

引用次数: 1

Phase-based scheduling and thread migration for heterogeneous multicore processors 异构多核处理器的基于阶段的调度和线程迁移

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370913

L. Sawalha, R. D. Barnes

引用次数: 2

Multi2Sim: A simulation framework for CPU-GPU computing Multi2Sim:一个CPU-GPU计算的仿真框架

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370865

R. Ubal, B. Jang, Perhaad Mistry, Dana Schaa, D. Kaeli

引用次数: 467

Making it practical and effective: Fast and precise May-Happen-in-Parallel analysis 使其实用和有效:快速和精确的可能发生的并行分析

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370900

Congming Chen, Wei Huo, Xiaobing Feng

引用次数: 4

Inference and declaration of independence: Impact on deterministic task parallelism 推理和独立性声明:对确定性任务并行性的影响

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370892

Foivos S. Zakkak, Dimitrios Chasapis, Polyvios Pratikakis, A. Bilas, Dimitrios S. Nikolopoulos

引用次数: 6

Efficient techniques for predicting cache sharing and throughput 预测缓存共享和吞吐量的有效技术

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370861

Andreas Sandberg, D. Black-Schaffer, Erik Hagersten

引用次数: 17