2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)最新文献_第4页

Making data prefetch smarter: Adaptive prefetching on POWER7 使数据预取更智能:POWER7上的自适应预取

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370837

Víctor Jiménez, R. Gioiosa, F. Cazorla, A. Buyuktosunoglu, P. Bose, F. O'Connell

{"title":"Making data prefetch smarter: Adaptive prefetching on POWER7","authors":"Víctor Jiménez, R. Gioiosa, F. Cazorla, A. Buyuktosunoglu, P. Bose, F. O'Connell","doi":"10.1145/2370816.2370837","DOIUrl":"https://doi.org/10.1145/2370816.2370837","url":null,"abstract":"Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow the user to change some of their parameters. The prefetcher, however, is usually enabled in a default configuration during system bring-up and dynamic reconfiguration of the prefetch engine is not an autonomic feature of current machines. Conceptually, however, it is easy to infer that commonly used prefetch algorithms, when applied in a fixed mode will not help performance in many cases. In fact, they may actually degrade performance due to useless bus bandwidth consumption and cache pollution. In this paper, we present an adaptive prefetch scheme that dynamically modifies the prefetch settings in order to adapt to the workload requirements. We implement and evaluate adaptive prefetching in the context of an existing, commercial processor, namely the IBM POWER7. Our adaptive prefetch mechanism improves performance with respect to the default prefetch setting up to 2.7X and 30% for single-threaded and multiprogrammed workloads, respectively.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133053636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 55

RISE: Improving the streaming processors reliability against soft errors in GPGPUs RISE:提高流处理器对gpgpu软错误的可靠性

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370846

Jingweijia Tan, Xin Fu

{"title":"RISE: Improving the streaming processors reliability against soft errors in GPGPUs","authors":"Jingweijia Tan, Xin Fu","doi":"10.1145/2370816.2370846","DOIUrl":"https://doi.org/10.1145/2370816.2370846","url":null,"abstract":"With hundreds of cores integrated into a single chip, the general-purpose computing on graphic processing units (GPGPUs) provide high computing power to accelerate parallel applications. However, they are prone to manifest high soft-error vulnerability due to the lack of fault detection and tolerance. Especially, streaming processors become the reliability hot-spot in GPGPUs. This paper explores two opportunistic soft-error detection techniques to cost-effectively improve the streaming processors reliability. Observing that the streaming processors are not fully utilized during the branch divergence and pipeline stalls caused by the long latency operations, we propose to Recycle the streaming processors Idle time for Soft-Error detection (RISE) and obtain the good fault coverage with negligible performance degradation. RISE is composed of full-RISE and partial-RISE. Full-RISE selectively triggers the redundancy for a set of warps so that leverages the fully idled streaming processors during the pipeline stall time for the error detection. Partial-RISE performs the redundancy for a number of threads in certain warps using the partially idled streaming processors during the branch divergence. Our experimental results show that RISE shows strong capability in improving the SPs soft-error reliability by 43% with negligible (e.g. 4%) performance loss.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122803405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Hardware acceleration in the IBM PowerEN processor: architecture and performance IBM PowerEN处理器中的硬件加速:体系结构和性能

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370872

A. Krishna, T. Heil, Nicholas Lindberg, F. Toussi, Steven P. Vanderwiel

引用次数: 37

Transactional event profiling in a best-effort hardware transactional memory system 尽力而为的硬件事务性内存系统中的事务性事件分析

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370904

Matthew Gaudet, J. N. Amaral

引用次数: 0

Design of a storage processing unit

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370906

Peng Li, Kevin Gomez, D. Lilja

{"title":"Design of a storage processing unit","authors":"Peng Li, Kevin Gomez, D. Lilja","doi":"10.1145/2370816.2370906","DOIUrl":"https://doi.org/10.1145/2370816.2370906","url":null,"abstract":"Researchers showed that performing computation directly on storage devices improves system performance in terms of energy consumption and processing time. For example, Riedel et al. [2] proposed an active disk which performs computation using the processor in a hard disk drive (HDD). Their experimental results showed that the active disk-based system had a factor of 2x performance improvement [2]. However, because the performance gap between the HDDs and CPUs becomes larger and larger, the active disk-based improvement is quite limited. As the role of flash memory increases in storage architectures, solid-state drives (SSDs) have gradually displaced the HDDs with higher access performance and lower power consumption. Researchers also proposed an active flash, which performs computation using a controller in the SSD [1]. However, the SSD controller needs to implement a flash translation layer to make the SSD as an emulated HDD for most operating systems. It also needs to communicate with a host interface to transfer required data. The additional computation power can be utilized is quite limited. To maximize the computation power on the SSD, we propose a processor design called storage processing unit (SPU).","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123398307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

PS-Dir: A scalable two-level directory cache PS-Dir:可扩展的两级目录缓存

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370891

J. Valls, Alberto Ros, J. Sahuquillo, M. E. Gómez, J. Duato

引用次数: 14

Energy-efficient cache partitioning for future CMPs 未来cmp的高效缓存分区

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370898

Karthik T. Sundararajan, Timothy M. Jones, N. Topham

引用次数: 7

Database analytics acceleration using FPGAs 使用fpga的数据库分析加速

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370874

Bharat Sukhwani, Hong Min, Mathew S. Thoennes, Parijat Dube, B. Iyer, B. Brezzo, D. Dillenberger, S. Asaad

{"title":"Database analytics acceleration using FPGAs","authors":"Bharat Sukhwani, Hong Min, Mathew S. Thoennes, Parijat Dube, B. Iyer, B. Brezzo, D. Dillenberger, S. Asaad","doi":"10.1145/2370816.2370874","DOIUrl":"https://doi.org/10.1145/2370816.2370874","url":null,"abstract":"Business growth and technology advancements have resulted in growing amounts of enterprise data. To gain valuable business insight and competitive advantage, businesses demand the capability of performing real-time analytics on such data. This, however, involves expensive query operations that are very time consuming on traditional CPUs. Additionally, in traditional database management systems (DBMS), the CPU resources are dedicated to mission-critical transactional workloads. Offloading expensive analytics query operations to a co-processor can allow efficient execution of analytics workloads in parallel with transactional workloads. In this paper, we present a Field Programmable Gate Array (FPGA) based acceleration engine for database operations in analytics queries. The proposed solution provides a mechanism for a DBMS to seamlessly harness the FPGA compute power without requiring any changes in the application or the existing data layout. Using a software-programmed query control block, the accelerator can be tailored to execute different queries without reconfiguration. Our prototype is implemented in a PCIe-attached FPGA system and is integrated into a commercial DBMS platform. The results demonstrate up to 94% CPU savings on real customer data compared to the baseline software cost with up to an order of magnitude speedup in the offloaded computations and up to 6.2× improvement in end-to-end performance.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127458462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 91

Riposte: A trace-driven compiler and parallel VM for vector code in R 一个跟踪驱动的编译器和并行VM，用于R中的矢量代码

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370825

Justin Talbot, Zach DeVito, P. Hanrahan

{"title":"Riposte: A trace-driven compiler and parallel VM for vector code in R","authors":"Justin Talbot, Zach DeVito, P. Hanrahan","doi":"10.1145/2370816.2370825","DOIUrl":"https://doi.org/10.1145/2370816.2370825","url":null,"abstract":"There is a growing utilization gap between modern hardware and modern programming languages for data analysis. Due to power and other constraints, recent processor design has sought improved performance through increased SIMD and multi-core parallelism. At the same time, high-level, dynamically typed languages for data analysis have become popular. These languages emphasize ease of use and high productivity, but have, in general, low performance and limited support for exploiting hardware parallelism. In this paper, we describe Riposte, a new runtime for the R language, which bridges this gap. Riposte uses tracing, a technique commonly used to accelerate scalar code, to dynamically discover and extract sequences of vector operations from arbitrary R code. Once extracted, we can fuse traces to eliminate unnecessary memory traffic, compile them to use hardware SIMD units, and schedule them to run across multiple cores, allowing us to fully utilize the available parallelism on modern shared-memory machines. Our evaluation shows that Riposte can run vector R code near the speed of hand-optimized C, 5–50× faster than the open source implementation of R, and can also linearly scale to 32 cores for some tasks. Across 12 different workloads we achieve an overall average speed-up of over 150× without explicit programmer parallelization.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131441635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Coalition Threading: Combining traditional and non-traditional parallelism to maximize scalability 联盟线程:结合传统和非传统的并行性来最大化可伸缩性

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370857

M. Kamruzzaman, S. Swanson, D. Tullsen

引用次数: 0