Energy-efficient cache partitioning for future CMPs

Abstract

The demand for high performance computing systems requires processor vendors to increase the number of cores per chip multiprocessor (CMP). However, as their number grows, the core-to-way ratio in the last level cache (LLC) increases, presenting problems to existing cache partitioning techniques which require more ways than cores. Further, effective energy management of the LLC becomes increasingly important due to its size. In this paper we propose an LLC energy-saving scheme for high-performance, many-core processors. It partitions the data within the cache into shared and private regions. Applications only access the ways containing the type of data that they require, realising dynamic energy savings. Any ways that are not within the shared or private regions can be turned off to save static energy.