{"title":"Application of CMOS-Compatible Micro-Hotplates for In-situ Process Monitors","authors":"J. Suehle, M. Gaitan","doi":"10.1109/IWLR.1992.657994","DOIUrl":"https://doi.org/10.1109/IWLR.1992.657994","url":null,"abstract":"A CMOS-compatible micromechanical structure that can be used as an in-situ sensor for monitoring and controlling the deposition of films is reported. This micro-hotplate structure is fabricated by the micromachining of commercial CMOS-technology wafers or chips and the deposition of additional films. This device is comprised of a polysilicon resistor for heating, an aluminum plate for temperature sensing, and four top aluminum contacts that provide electrical connection to sensing materials or to films that are being deposited. Arrays of micro-hotplates have been fabricated and used to study film growth at several substrate temperatures. A matrix of experiments can be performed during one deposition cycle using such an array of structures. Examples will be presented using the microhotplate: to monitor substrate temperature during aluminum sputtering, to monitor film resistivity during deposition, and to sense the presence of gas species.","PeriodicalId":395564,"journal":{"name":"International Report on Wafer Level Reliability Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132733564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Building In Reliability For Packaging And Assembly","authors":"C. Shirley","doi":"10.1109/IWLR.1992.657985","DOIUrl":"https://doi.org/10.1109/IWLR.1992.657985","url":null,"abstract":"Rapidly evolving package technology, especially plastic package technology, combined with shortening silicon process and product development cycles, demands increasingly rapid integration of package technology with silicon technology. On the other hand, package reliability evaluation still requires repeated cycles of fabrication, environmental test, and analysis. This forces parallel, modular, highly accelerated evaluation of the major reliability interactions between silicon and package. We survey the major technology trends, and how these affect siliconlpackage interactions inportant to reliability. Development cycle time may be reduced by replacing 85/85 with HAST and by using assemblyoriented test chips. A key area for future development is the development of models for the prediction of reliability, which will reduce the testing required.","PeriodicalId":395564,"journal":{"name":"International Report on Wafer Level Reliability Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124789734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Customer and Summary Report Management Acceptance Of Bir Group Discussion","authors":"B. Vasquez, D. Crook","doi":"10.1109/IWLR.1992.658011","DOIUrl":"https://doi.org/10.1109/IWLR.1992.658011","url":null,"abstract":"","PeriodicalId":395564,"journal":{"name":"International Report on Wafer Level Reliability Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126134349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wafer Level IC Burn-in As A Step Towards Bir","authors":"J. Miller, V. Soorholtz, B. Vesquez","doi":"10.1109/IWLR.1992.657999","DOIUrl":"https://doi.org/10.1109/IWLR.1992.657999","url":null,"abstract":"","PeriodicalId":395564,"journal":{"name":"International Report on Wafer Level Reliability Workshop","volume":"433 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Forecast Of The Gate Oxide Reliability On The Wafer Level","authors":"B. Lisenker","doi":"10.1109/IWLR.1992.657997","DOIUrl":"https://doi.org/10.1109/IWLR.1992.657997","url":null,"abstract":"","PeriodicalId":395564,"journal":{"name":"International Report on Wafer Level Reliability Workshop","volume":"603 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116172896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}