International Conference on High Performance Embedded Architectures and Compilers最新文献_第2页

Fast modeling of shared caches in multicore systems 多核系统共享缓存的快速建模

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944885

David Eklov, D. Black-Schaffer, Erik Hagersten

引用次数: 62

DDM-VMc: the data-driven multithreading virtual machine for the cell processor DDM-VMc:用于单元处理器的数据驱动多线程虚拟机

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944869

Samer Arandi, P. Evripidou

引用次数: 16

Parallel points-to analysis for multi-core machines 多核机器的并行点分析

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944872

Marcus Edvinsson, Jonas Lundberg, Welf Löwe

引用次数: 21

SWEEP: evaluating computer system energy efficiency using synthetic workloads SWEEP:使用合成工作负荷评估计算机系统的能源效率

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944886

Kristof Du Bois, T. Schaeps, Stijn Polfliet, Frederick Ryckbosch, L. Eeckhout

{"title":"SWEEP: evaluating computer system energy efficiency using synthetic workloads","authors":"Kristof Du Bois, T. Schaeps, Stijn Polfliet, Frederick Ryckbosch, L. Eeckhout","doi":"10.1145/1944862.1944886","DOIUrl":"https://doi.org/10.1145/1944862.1944886","url":null,"abstract":"Energy efficiency is a key design concern in contemporary processor and system design, in the embedded domain as well as in the enterprise domain. The focus on energy efficiency has led to a number of power benchmarking methods recently. For example, EEMBC released EnergyBench and SPEC released SPECpower to quantify a system's energy efficiency; also academics have proposed power benchmarks, such as JouleSort. A major limitation for each of these proposals is that they are tied to a specific benchmark, and hence, they provide limited insight with respect to why one system may be more energy-efficient than another.\u0000 This paper proposes SWEEP, Synthetic Workloads for Energy Efficiency and Performance evaluation, a framework for generating synthetic workloads with specific behavioral characteristics. We employ SWEEP to generate a wide range of synthetic workloads while varying the instruction mix, ILP, memory access patterns, and I/O-intensiveness; and we use SWEEP to evaluate the energy efficiency of commercial computer systems across the workload space and learn about how the energy efficiency of a computer system is tied to its workload's characteristics.\u0000 This paper also presents the Energy-Delay Diagram (EDD), a novel method for visualizing energy efficiency. The EDD clearly illustrates the energy versus performance trade-off, and provides more intuitive insight than the traditionally used EDP and ED2P metrics.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128323651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

High throughput data redundancy removal algorithm with scalable performance 具有可扩展性能的高吞吐量数据冗余去除算法

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944877

Souvik Bhattacherjee, A. Narang, Vikas K. Garg

{"title":"High throughput data redundancy removal algorithm with scalable performance","authors":"Souvik Bhattacherjee, A. Narang, Vikas K. Garg","doi":"10.1145/1944862.1944877","DOIUrl":"https://doi.org/10.1145/1944862.1944877","url":null,"abstract":"The ever growing need to process and analyze massive amounts of data from diverse sources such as telecom call data records, telescope imagery, web pages, stock markets, medical records and other domains has triggered worldwide research in data intensive computing. A key requirement here involves removing redundancy from data, as this enhances the compute efficiency for downstream data processing. These application domains have an intense need for high throughput data deduplication for huge volumes of data flowing at the rate of 1 GB/s or more. In this paper, we present the design of a novel parallel data redundancy removal algorithm. We also present a queueing theoretic analysis to optimize the throughput of our parallel algorithm on multi-core architectures. For 500M records, our parallel algorithm can perform complete deduplication in 255s, on 16 core Intel Xeon 5570 architecture. This gives a throughput of around 2M records/s. For 2048 byte records, we achieve a throughput of 0.81 GB/s. To the best of our knowledge, this is the highest throughput for data redundancy removal on such massive datasets. We also demonstrate strong and weak scalability of our algorithm for both multi-core Power6 and Intel Xeon 5570 architectures.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129654288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Extended histories: improving regularity and performance in correlation prefetchers 扩展历史:改善相关预取器的规律性和性能

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944875

R. Manikantan, Ramaswamy Govindarajan, K. Rajan

{"title":"Extended histories: improving regularity and performance in correlation prefetchers","authors":"R. Manikantan, Ramaswamy Govindarajan, K. Rajan","doi":"10.1145/1944862.1944875","DOIUrl":"https://doi.org/10.1145/1944862.1944875","url":null,"abstract":"Data Prefetchers identify and make use of any regularity present in the history/training stream to predict future references and prefetch them into the cache. The training information used is typically the primary misses seen at a particular cache level, which is a filtered version of the accesses seen by the cache. In this work we demonstrate that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers. In addition to empirical evaluation, we use the information theoretic metric entropy, to quantify the regularity present in extended histories. Entropy measurements indicate that extended histories are more regular than the default primary miss only training stream. Entropy measurements also help corroborate our empirical findings.\u0000 With extended histories, further benefits can be achieved by triggering prefetches during secondary misses also. In this paper we explore the design space of extended prefetch histories and alternative prefetch trigger points for delta correlation prefetchers. We observe that different prefetch schemes benefit to a different extent with extended histories and alternative trigger points. Also the best performing design point varies on a per-benchmark basis. To meet these requirements, we propose a simple adaptive scheme that identifies the best performing design point for a benchmark-prefetcher combination at runtime.\u0000 In SPEC2000 benchmarks, using all the L2 accesses as history for prefetcher improves the performance in terms of both IPC and misses reduced over techniques that use only primary misses as history. The adaptive scheme improves the performance of CZone prefetcher over Baseline by 4.6% on an average. These performance gains are accompanied by a moderate reduction in the memory traffic requirements.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130425940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

GLOpenCL: OpenCL support on hardware- and software-managed cache multicores OpenCL支持硬件和软件管理的多核缓存

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944868

Konstantis Daloukas, C. Antonopoulos, Nikolaos Bellas

{"title":"GLOpenCL: OpenCL support on hardware- and software-managed cache multicores","authors":"Konstantis Daloukas, C. Antonopoulos, Nikolaos Bellas","doi":"10.1145/1944862.1944868","DOIUrl":"https://doi.org/10.1145/1944862.1944868","url":null,"abstract":"OpenCL is an industry supported standard for writing programs that execute on multicore platforms as well as on accelerators, such as GPUs or the SPEs of the Cell B.E. In this paper we introduce GLOpenCL, a unified development framework which supports OpenCL on both homogeneous, shared memory, as well as on heterogeneous, distributed memory multicores. The framework consists of a compiler, based on the LLVM compiler infrastructure, and a run-time library, sharing the same basic architecture across all target platforms. The compiler recognizes OpenCL constructs, performs source-to-source code transformations targeting both efficiency and semantic correctness, and adds calls to the run-time library. The latter offers functionality for work creation, management and execution, as well as for data transfers. We evaluate our framework using benchmarks from the distributions of OpenCL implementations by hardware vendors. We find that our generic system performs comparably or better than customized, platform-specific vendor distributions. OpenCL is designed and marketed as a write-once run-anywhere software development framework. However, the standard leaves enough room for target platform specific optimizations. Our experimentation with different, customized implementations of kernels reveals that optimized, hardware mapped implementations are both possible and necessary in the context of OpenCL -- especially on non-conventional multicores -- if performance is considered a higher priority than programmability.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130202220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Moore's law implications on energy reduction 摩尔定律对能量减少的影响

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944864

Antonio González

引用次数: 0

Automated empirical tuning of scientific codes for performance and power consumption 性能和功耗的科学代码的自动经验调优

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944880

Faizur Rahman, Jichi Guo, Qing Yi

{"title":"Automated empirical tuning of scientific codes for performance and power consumption","authors":"Faizur Rahman, Jichi Guo, Qing Yi","doi":"10.1145/1944862.1944880","DOIUrl":"https://doi.org/10.1145/1944862.1944880","url":null,"abstract":"Automatic empirical tuning of compiler optimizations has been widely used to achieve portable high performance for scientific applications. However, as power dissipation becomes increasingly important in modern architecture design, few have attempted to empirically tune optimization configurations to reduce the power consumption of applications. We provide an automated empirical tuning framework that can be configured to optimize for both performance and energy efficiency. In particular, we extensively parameterize the configuration of a large number of compiler optimizations, including loop parallelization, blocking, unroll-and-jam, array copying, scalar replacement, strength reduction, and loop unrolling. We then use hardware counters combined with elapsed time to estimate both the performance and the power consumption of differently optimized code to automatically discover desirable configurations for these optimizations. We use a power meter to verify our tuning results on two multi-core computers and show that our approach can effectively achieve a balanced performance and energy efficiency on modern CMP machines.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130232171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

Cost-aware function migration in heterogeneous systems 异构系统中具有成本意识的功能迁移

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944883

M. Kicherer, R. Buchty, Wolfgang Karl

引用次数: 21