International Conference on High Performance Embedded Architectures and Compilers最新文献

Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches 缓存均衡器:芯片多处理器分布式共享缓存的放置机制

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944889

Mohammad Hammoud, Sangyeun Cho, R. Melhem

引用次数: 10

Speculatively vectorized bytecode 推测向量化字节码

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944871

Erven Rohou, Sergei Dyshel, Dorit Nuzman, Ira Rosen, K. Williams, Albert Cohen, A. Zaks

{"title":"Speculatively vectorized bytecode","authors":"Erven Rohou, Sergei Dyshel, Dorit Nuzman, Ira Rosen, K. Williams, Albert Cohen, A. Zaks","doi":"10.1145/1944862.1944871","DOIUrl":"https://doi.org/10.1145/1944862.1944871","url":null,"abstract":"Diversity is a confirmed trend of computing systems, which present a complex and moving target to software developers. Virtual machines and just-in-time compilers have been proposed to mitigate the complexity of these systems. They do so by offering a single and stable abstract machine model thereby hiding architectural details from programmers.\u0000 SIMD capabilities are common among current and expected computing systems. Efficient exploitation of SIMD instructions has become crucial for the performance of many applications. Existing auto-vectorizers operate within traditional static optimizing compilers, and use details about the target architecture when generating SIMD instructions. Unfortunately, auto-vectorizers are currently too complex to be included in a constrained Just-In-Time (JIT) environment.\u0000 In this paper we propose Vapor SIMD: a speculative approach for effective just-in-time vectorization. Vapor SIMD first applies complex ahead-of-time techniques to vectorize source code and produce bytecode of a standard portable format. Advanced JIT compilers can then quickly tailor this bytecode to exploit SIMD capabilities of appropriate platforms, yielding up to 14.7x and 11.8x speedups on x86 and PowerPC platforms (including JIT-compilation time). JIT compilers can also seamlessly revert to non-vector code, in the absence of SIMD capabilities or in the case of a third-party non-vectorizing JIT compiler, yielding 93% or more of the original performance.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114501512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A workload-aware mapping approach for data-parallel programs 数据并行程序的工作负载感知映射方法

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944881

Dominik Grewe, Zheng Wang, M. O’Boyle

引用次数: 50

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors 在平铺式芯片多处理器上多线程执行的noc感知缓存设计

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944891

Ahmed Abousamra, A. Jones, R. Melhem

{"title":"NoC-aware cache design for multithreaded execution on tiled chip multiprocessors","authors":"Ahmed Abousamra, A. Jones, R. Melhem","doi":"10.1145/1944862.1944891","DOIUrl":"https://doi.org/10.1145/1944862.1944891","url":null,"abstract":"In chip multiprocessors (CMPs), data access latency depends on the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access latency is vital to achieving performance improvements and scalability of threaded applications. Multithreaded applications generally exhibit sharing of data among the program threads, which generates coherence and data traffic on the NoC.\u0000 Many NoC designs exploit communication locality to reduce communication latency by configuring special fast paths on which communication is faster than the rest of the NoC. Communication patterns are directly affected by the cache organization. However, many cache organizations are designed in isolation of the underlying NoC or assume a simple NoC design, thus possibly missing optimization opportunities. In this work, we present a NoC-aware cache design that creates a symbiotic relationship between the NoC and cache to reduce data access latency, improve utilization of cache capacity, and improve overall system performance. Specifically, considering a NoC designed to exploit communication locality, we design a Unique Private caching scheme that promotes locality in communication patterns. In turn, the NoC exploits this locality to allow fast access to remote data, thus reducing the need for data replication and allowing better utilization of cache capacity. The Unique Private cache stores the data mostly used by a processor core in its locally accessible cache bank, while leveraging dedicated high speed circuits in the interconnect to provide remote cores with fast access to shared data. Simulations of a suite of scientific and commercial workloads show that our proposed design achieves a speedup of 14% and 16% on a 16-core and a 64-core CMP, respectively, over the state-of-the-art NoC-Cache co-designed system which also exploits communication locality in multithreaded applications.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130180148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

RVC: a mechanism for time-analyzable real-time processors with faulty caches RVC:具有故障缓存的可分析时间的实时处理器的机制

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944878

J. Abella, E. Quiñones, F. Cazorla, Yiannakis Sazeides, M. Valero

引用次数: 19

Runtime parallelization of legacy code on a transactional memory system 事务性内存系统上遗留代码的运行时并行化

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944882

M. DeVuyst, D. Tullsen, S. Kim

引用次数: 31

PetaBricks: a language and compiler based on autotuning petabbricks:一种基于自动调优的语言和编译器

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944865

Saman P. Amarasinghe

引用次数: 10

TypeCastor: demystify dynamic typing of JavaScript applications TypeCastor:揭开JavaScript应用程序动态类型的神秘面纱

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944873

Shisheng Li, B. Cheng, Xiao-Feng Li

{"title":"TypeCastor: demystify dynamic typing of JavaScript applications","authors":"Shisheng Li, B. Cheng, Xiao-Feng Li","doi":"10.1145/1944862.1944873","DOIUrl":"https://doi.org/10.1145/1944862.1944873","url":null,"abstract":"Dynamic typing is a barrier for JavaScript applications to achieve high performance. Compared with statically typed languages, the major overhead of dynamic typing comes from runtime type resolution and runtime property lookup. Common folks' belief is that the traditional static compilation techniques are no longer effective for dynamic languages. The best known JavaScript engines such as Mozilla TraceMonkey and Chrome V8 have developed non-traditional techniques to reduce the runtime overhead. This paper describes TypeCastor, a new JavaScript engine that tries to investigate where and how much the dynamism really is in JavaScript applications, thus to demystify their dynamic typing behavior. To verify our findings, we evaluate TypeCastor with SunSpider benchmark. For type resolution, we find 99% of all the primitive type instances can be statically identified before the program execution. For object property lookup, more than 97% of all runtime property accesses can be satisfied by inline cache. These data mean that the representative JavaScript applications are not that dynamic as people expect, although the language provides the flexible dynamism supports. Though not developed for pure performance, TypeCastor achieves 5.6% and 12.7% higher scores compared to current Chrome V8 and Mozilla TraceMonkey engines respectively.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"102 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123247081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A stream-computing extension to OpenMP OpenMP的流计算扩展

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944867

Antoniu Pop, Albert Cohen

引用次数: 66

Directly characterizing cross core interference through contention synthesis 通过争用综合直接表征交叉芯干扰

International Conference on High Performance Embedded Architectures and Compilers Pub Date : 2011-01-24 DOI: 10.1145/1944862.1944887

Jason Mars, Lingjia Tang, M. Soffa

{"title":"Directly characterizing cross core interference through contention synthesis","authors":"Jason Mars, Lingjia Tang, M. Soffa","doi":"10.1145/1944862.1944887","DOIUrl":"https://doi.org/10.1145/1944862.1944887","url":null,"abstract":"In this paper, we present a direct methodology and framework for the measurement and characterization of an application's cross-core interference sensitivity on multicore microarchitectures. While prior works use indirect indicators, such as last level cache miss rate, to infer an application's cross-core interference sensitivity, our approach is direct, in that it characterizes the application's cross-core interference sensitivity using the performance impact due to actual contention. Our methodology and framework, the Cross-core interference Profiling Environment, or CiPE, is composed of a lightweight runtime environment on which a host application runs, along with a carefully designed contention synthesis engine that executes on a neighboring core. CiPE manipulates the co-running contention synthesis engine, while monitoring and analyzing the resulting dynamic impact on the host application.\u0000 CiPE is able to characterize the cross-core interference sensitivity of the entire application, its individual phases, or source level code regions. To demonstrate the effectiveness of CiPE, we use CiPE characterizations to address two pressing problems. First, we use CiPE characterizations to perform contention conscious batch scheduling that minimizes cross-core interference, resulting in a 12% performance improvment on average when applied to the SPEC2006 benchmark suite, and beyond 20% in the case of mcf and omnetpp. Second, we use CiPE to design a performance analysis tool that is capable identifying contentious bottlenecks in application code.","PeriodicalId":394008,"journal":{"name":"International Conference on High Performance Embedded Architectures and Compilers","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125441074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 69