2018 Ninth International Green and Sustainable Computing Conference (IGSC)最新文献_第2页

Multiobjective Evaluation and Optimization of CMT-bone on Intel Knights Landing 英特尔骑士登陆CMT-bone多目标评价与优化

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752152

M. Gadou, Tania Banerjee-Mishra, Meenakshi Arunachalam, G. Shipman, S. Ranka

引用次数: 0

Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery 超低电压时钟优化的多电压域配电网

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752126

Md. Shazzad Hossain, I. Savidis

{"title":"Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery","authors":"Md. Shazzad Hossain, I. Savidis","doi":"10.1109/IGCC.2018.8752126","DOIUrl":"https://doi.org/10.1109/IGCC.2018.8752126","url":null,"abstract":"In this paper, the co-design of the clock and power delivery networks is proposed for ultra-low power IoT applications operating in sub-threshold. A distributed, multi-voltage domain and hierarchical power distribution network is proposed to deliver current to the clock buffers, registers, and combinational circuits in local clock distribution networks. The variation of the clock skew, setup time, hold time, and clock-to-q delay are analyzed under process and supply voltage variation. The effect on timing due to supply and process variation is analyzed for a target operating voltage and frequency of, respectively, 250 mV and 2 MHz in a 130 nm CMOS technology. The minimum clock period, skew, and insertion delay are reduced to, respectively, 0.74×, 0.52×, and 0.79× when optimized sub-threshold buffers are implemented, as compared and normalized to a clock network that includes non-optimized buffers. In addition, the co-designed clock and power networks were resilient to as much as 10% variation in the supply voltage when the proposed multi-voltage domain and distributed power distribution network is used with the optimized clock buffers.","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125136738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

All-day Workshop: Power/Energy Management at Extreme Scale Workshop 全天研讨会:在极端规模的电源/能源管理研讨会

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/igcc.2018.8752154

B. Rountree

引用次数: 0

Using Machine Learning to reduce the energy wasted in Volunteer Computing Environments 利用机器学习减少志愿者计算环境中的能源浪费

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752115

A. McGough, M. Forshaw, John Brennan, N. A. Moubayed, Stephen Bonner

引用次数: 3

Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory 通过抑制深度缩放相变存储器中的干扰串扰提高可持续性

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752107

Seyed Mohammad Seyedzadeh, A. Jones, R. Melhem

{"title":"Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory","authors":"Seyed Mohammad Seyedzadeh, A. Jones, R. Melhem","doi":"10.1109/IGCC.2018.8752107","DOIUrl":"https://doi.org/10.1109/IGCC.2018.8752107","url":null,"abstract":"Phase change memory (PCM) is a popular emerging technology for next generation systems. PCM provides advantages compared to conventional memories such as DRAM and Flash including reduced static energy, density advantages over DRAM, and performance and endurance advantages over Flash. Some limitations of PCM, including high dynamic energy and limited endurance can be improved through intelligent encoding. Unfortunately, the additional density benefits achieved through technology scaling increases the proximity between cells and for technologies below 22nm, which can lead to inadvertent writing, referred to as write disturbance, both within the active wordline (i.e., row) and across neighboring wordlines (rows). Write disturbance results in significant system inefficiency to check and rewrite disturbed cells. In this paper, we develop a multi-tiered compression technique that compresses by a small amount (e.g., 40- or 56-bits of a 512-bit block) for >94% of cachelines stored into memory (e.g., during eviction) without disturbing data locality vital for optimizing PCM writes. Using this recovered space, we design a one-to-one mapping that probabilistically detects the cells likely to disturb neighboring cells. Using encoding, correction pointers, and a hybrid approach, we can reduce the instances of write disturbance. Due to using reclaimed bits for encoding, the proposed technique requires only five (5) additional auxiliary bits per 512-bit cacheline, minimizing the embodied energy (fabrication) overhead to mitigate write disturbance. Our experimental tests shows that the proposed technique successfully reduces the number of disturbed cells, which can be directly translated to the number of extra write and read operations, required for disturbance error mitigation. Specifically, our technique improves performance, endurance and write energy by 47%, 42% and 36% versus the leading approach with minimal (circa 1%) increases to embodied energy.","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132567367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A systematic Way for Determining CO2 Obligation in Power Systems 确定电力系统二氧化碳负荷的系统方法

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752156

Mahdi Rouholamini, Carol J. Miller

引用次数: 0

IGSC 2018 PhD Workshop on Energy-Efficient and Secure Computing Systems IGSC 2018节能与安全计算系统博士研讨会

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/igcc.2018.8752160

引用次数: 0

IGSC 2018 Special Track on Sustainable Cyber-Physical Systems IGSC 2018可持续信息物理系统特别专题

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/igcc.2018.8752163

引用次数: 0

Information, Quantum Mechanics, and the Universe 信息、量子力学和宇宙

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752111

J. Levy

引用次数: 0

Achieving Secure, Reliable, and Sustainable Next Generation Computing Memories 实现安全、可靠和可持续的下一代计算存储器

2018 Ninth International Green and Sustainable Computing Conference (IGSC) Pub Date : 2018-10-01 DOI: 10.1109/IGCC.2018.8752128

Donald Kline, A. Jones

{"title":"Achieving Secure, Reliable, and Sustainable Next Generation Computing Memories","authors":"Donald Kline, A. Jones","doi":"10.1109/IGCC.2018.8752128","DOIUrl":"https://doi.org/10.1109/IGCC.2018.8752128","url":null,"abstract":"The design of next generation memory systems for increasingly large datasets is primarily being pursued through two fronts: (1) The continued progression of process scaling for conventional memories such as DRAM and Flash and (2) the commercialization of emerging non-volatile memory technologies including Phase Change, Resistive, and Spin-Torque Transfer Magnetic memories. Both avenues have illuminated reliability concerns including crosstalk-based disturbance and limited endurance. Crosscutting to these issues are challenges in maintaining or improving performance and operational energy. However, an emerging critical challenge is understanding, quantifying, and optimizing the sustainability of these memories in the face of exponentially increasing embodied costs (including energy and carbon emissions) due to the fabrication approaches of increasingly smaller nodes and processes for new technologies.I have contributed several approaches to different layers of this effort. For example, I designed low-energy network-on-chip (NoC) buffers for many-core systems using domain-wall memories. To support fault tolerance in these memory technologies, I have designed several fault map approaches. Based on knowledge of the types of faults in particular memory technologies and in using these fault maps, I have designed low-overhead encoding schemes to avoid faults and developed methods to increase memory lifetime. I have also developed collaboratively designed approaches that integrate fault tolerance with security. Finally, I have demonstrated the energy and environmental impacts of different memory design choices including technologies and fault tolerance approaches with holistic energy tradeoff analyses. My work provides advances in architectures, fault tolerance, security, and sustainability of these next generation memory systems.","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125249725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0