Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory

Seyed Mohammad Seyedzadeh, A. Jones, R. Melhem
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引用次数: 3

Abstract

Phase change memory (PCM) is a popular emerging technology for next generation systems. PCM provides advantages compared to conventional memories such as DRAM and Flash including reduced static energy, density advantages over DRAM, and performance and endurance advantages over Flash. Some limitations of PCM, including high dynamic energy and limited endurance can be improved through intelligent encoding. Unfortunately, the additional density benefits achieved through technology scaling increases the proximity between cells and for technologies below 22nm, which can lead to inadvertent writing, referred to as write disturbance, both within the active wordline (i.e., row) and across neighboring wordlines (rows). Write disturbance results in significant system inefficiency to check and rewrite disturbed cells. In this paper, we develop a multi-tiered compression technique that compresses by a small amount (e.g., 40- or 56-bits of a 512-bit block) for >94% of cachelines stored into memory (e.g., during eviction) without disturbing data locality vital for optimizing PCM writes. Using this recovered space, we design a one-to-one mapping that probabilistically detects the cells likely to disturb neighboring cells. Using encoding, correction pointers, and a hybrid approach, we can reduce the instances of write disturbance. Due to using reclaimed bits for encoding, the proposed technique requires only five (5) additional auxiliary bits per 512-bit cacheline, minimizing the embodied energy (fabrication) overhead to mitigate write disturbance. Our experimental tests shows that the proposed technique successfully reduces the number of disturbed cells, which can be directly translated to the number of extra write and read operations, required for disturbance error mitigation. Specifically, our technique improves performance, endurance and write energy by 47%, 42% and 36% versus the leading approach with minimal (circa 1%) increases to embodied energy.
通过抑制深度缩放相变存储器中的干扰串扰提高可持续性
相变存储器(PCM)是一种新兴的新一代系统技术。与DRAM和Flash等传统存储器相比,PCM具有诸多优势,包括静态能量降低、密度优于DRAM、性能和耐用性优于Flash。通过智能编码可以改善PCM的动态能量高、续航能力有限等缺点。不幸的是,通过技术缩放获得的额外密度优势增加了单元之间的接近度,对于低于22nm的技术,这可能导致在活动字线(即行)内和相邻字线(行)内的无意写入,称为写入干扰。写入干扰导致系统在检查和重写受到干扰的单元时效率低下。在本文中,我们开发了一种多层压缩技术,该技术可以将存储在内存中的cachelines(例如,在删除期间)压缩少量(例如,512位块中的40位或56位),而不会干扰对优化PCM写入至关重要的数据局部性。利用这个恢复的空间,我们设计了一个一对一的映射,以概率地检测可能干扰相邻细胞的细胞。使用编码、校正指针和混合方法,我们可以减少写干扰的实例。由于使用回收比特进行编码,所提出的技术每512位cacheline只需要5(5)个额外的辅助比特,最大限度地减少了隐含能量(制造)开销,以减轻写入干扰。我们的实验测试表明,所提出的技术成功地减少了干扰单元的数量,这可以直接转化为减少干扰误差所需的额外写入和读取操作的数量。具体来说,我们的技术提高了47%,42%和36%的性能,耐力和写入能量,而主要方法只增加了最小(约1%)的隐含能量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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