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2011 21st International Conference on Systems Engineering最新文献

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Heart Disease Classification Using Neural Network and Feature Selection 基于神经网络和特征选择的心脏病分类
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.80
A. Khemphila, V. Boonjing
{"title":"Heart Disease Classification Using Neural Network and Feature Selection","authors":"A. Khemphila, V. Boonjing","doi":"10.1109/ICSEng.2011.80","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.80","url":null,"abstract":"In this study, we introduces a classification approach using Multi-Layer Perceptron (MLP)with Back-Propagation learning algorithm and a feature selection algorithm along with biomedical test values to diagnose heart disease. Clinical diagnosis is done mostly by doctor's expertise and experience. But still cases are reported of wrong diagnosis and treatment. Patients are asked to take number of tests for diagnosis. In many cases, not all the tests contribute towards effective diagnosis of a disease. Our work is to classify the presence of heart disease with reduced number of attributes. Original, 13 attributes are involved in classify the heart disease. We use Information Gain to determine the attributes which reduces the number of attributes which is need to be taken from patients. The Artificial neural networks is used to classify the diagnosis of patients. Thirteen attributes are reduced to 8 attributes. The accuracy differs between 13 features and 8 features in training data set is 1.1% and in the validation data set is 0.82%.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 135
Reduction of Knowledge Representation Using Logic Minimization Techniques 使用逻辑最小化技术的知识表示约简
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.98
G. Borowik, T. Luba, D. Zydek
{"title":"Reduction of Knowledge Representation Using Logic Minimization Techniques","authors":"G. Borowik, T. Luba, D. Zydek","doi":"10.1109/ICSEng.2011.98","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.98","url":null,"abstract":"This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132801463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Acronym Expansion Via Hidden Markov Models 基于隐马尔可夫模型的缩略语展开
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.29
K. Taghva, Lakshmi Vyas
{"title":"Acronym Expansion Via Hidden Markov Models","authors":"K. Taghva, Lakshmi Vyas","doi":"10.1109/ICSEng.2011.29","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.29","url":null,"abstract":"In this paper, we report on design and implementation of a Hidden Markov Model (HMM) to extract acronyms and their expansions. We also report on the training of this HMM with Maximum Likelihood Estimation (MLE) algorithm using a set of examples. Finally, we report on our testing using standard recall and precision. The HMM achieves a recall and precision of 98% and 92% respectively.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128180089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
New Boolean Multivalued Logic System Simplifying Inferences in Flexible Styles 简化灵活样式推理的新布尔多值逻辑系统
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.27
Asami Sasaki, Kujira Suzuki, K. Sugimoto, Hisashi Suzuki
{"title":"New Boolean Multivalued Logic System Simplifying Inferences in Flexible Styles","authors":"Asami Sasaki, Kujira Suzuki, K. Sugimoto, Hisashi Suzuki","doi":"10.1109/ICSEng.2011.27","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.27","url":null,"abstract":"This article, by regarding the relative number of affirmative bits on an arbitrary finite sequence of bits as the truth value, defines a new multivalued logic system such that the set of logic formulae forms a Boolean algebra in contrast to other non-Boolean multivalued logic systems, which we call a Boolean multivalued logic system. This article also, for demonstrating compactly that the Boolean properties (in contrast to other multivalued logic systems) simplify multivalued inferences in flexible styles, shows several intuitively-understandable examples tracing biotic diversity such that, on the proposed logic system, we can easily handle semantic inferences verifying values of all bits of each logic formula, inductive inferences counting the relative numbers of affirmative bits for determination of truth values, and deductive inferences syntactically narrowing ranges of truth values.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123861281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Providing Strict QoS Guaranties for Flows with Time-varying Capacity Requirements 为容量时变的流提供严格的QoS保证
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.57
P. Swiatek, M. Drwal, A. Grzech
{"title":"Providing Strict QoS Guaranties for Flows with Time-varying Capacity Requirements","authors":"P. Swiatek, M. Drwal, A. Grzech","doi":"10.1109/ICSEng.2011.57","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.57","url":null,"abstract":"Many distributed applications require bandwidth provisioning to implement their functionality. A prominent example is a remote real-time monitoring service in e-health system, where a special type of emergency requests require strict guaranties regarding provided transmission rates. We consider the problem of network capacity sharing between two types of flows: standard best-effort flows and QoS-constrained flows. We derive distributed control algorithms for dynamic capacity allocation allowing to serve the QoS-constrained flows by preempting the best-effort flows. Such solution minimizes the amount of unused capacity. We also present how to estimate the capacity needed to deploy QoS-based application in a way to minimize the number of flow preemptions. The presented solution is evaluated in a simulation environment.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121164715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of Prognostic and Health Management Structure for UAV System 无人机系统预测与健康管理结构设计
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.11
Xinwei Li, Wenjin Zhang
{"title":"Design of Prognostic and Health Management Structure for UAV System","authors":"Xinwei Li, Wenjin Zhang","doi":"10.1109/ICSEng.2011.11","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.11","url":null,"abstract":"As high-tech weapon systems, the failure prediction and maintenance support of Unmanned Aerial Vehicle (UAV) have attracted more and more attention. The traditional concept has been changed by using Prognostic and Health Management (PHM) on UAV maintenance support. The realization of PHM has changed the mode of UAV maintenance. The original maintenance mode base on existing incident (maintenance after fault happened) and time related mode (regular maintenance) will be replaced by the new mode based on the state (according to the state). In this paper, the PHM method used for UAV maintenance has been discussed. And by building a structure of PHM system for UAV system, the maintenance support hardware and software architecture is proposed and analyzed for further application.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Older Opteron Outperforms the Newer Xeon: A Memory Intensive Application Study of Server Based Microprocessors 老Opteron优于新Xeon:基于服务器微处理器的内存密集型应用研究
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.74
W. Weerasuriya, D. Ranasinghe
{"title":"Older Opteron Outperforms the Newer Xeon: A Memory Intensive Application Study of Server Based Microprocessors","authors":"W. Weerasuriya, D. Ranasinghe","doi":"10.1109/ICSEng.2011.74","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.74","url":null,"abstract":"In this paper we describe the performance evaluation and comparison of a older \"dual processor dual core AMD Opteron\" server processor and a newer \"single processor quad core Intel Xeon\" server processor, on their performance in executing memory intensive applications. We evaluated the performance of the two micro-architectures by analyzing the results obtained from the respective microprocessor hardware performance monitoring counters. Our experiment results show that the older Opteron gives a better throughput than the newer Xeon. With this study we found that the older \"dual processor dual core AMD Opteron\" outperforms the newer \"single processor quad core Intel Xeon\" in executing memory intensive software applications.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of Parity Equations Using Right Eigenstructure Assignment 利用右特征结构赋值设计奇偶方程
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.73
M. Sumislawska, T. Larkowski, K. Burnham
{"title":"Design of Parity Equations Using Right Eigenstructure Assignment","authors":"M. Sumislawska, T. Larkowski, K. Burnham","doi":"10.1109/ICSEng.2011.73","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.73","url":null,"abstract":"System uncertainties, such as modelling errors, external disturbances etc. can impede the fault detection process. Therefore a need arises for robust fault diagnosis, where complete disturbance decoupling can be achieved. The main contribution of this paper is the design of a parity relation for robust fault detection using right eigenstructure assignment. Up to date the left eigenstructure assignment technique has been used for the design of first order disturbance decoupled parity relations. In many cases complete disturbance decoupling is not possible when using left eigenstructure assignment. Therefore, the proposed method utilises the right eigenstructure assignment technique for the purpose of robust fault detection. The novelty of the developed scheme is to replace the traditional asymptotically convergent state observer by a state observer, which converges in a predefined time. The proposed method is demonstrated to be equivalent to a parity relation of a user predefined order.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114186054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Implementation of a Video Compression Technique for High Definition Videos Implemented on a FPGA 基于FPGA的高清视频压缩技术的设计与实现
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.60
K. Shehata, A. Hashad, H. Husien, H. Fahmy
{"title":"Design and Implementation of a Video Compression Technique for High Definition Videos Implemented on a FPGA","authors":"K. Shehata, A. Hashad, H. Husien, H. Fahmy","doi":"10.1109/ICSEng.2011.60","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.60","url":null,"abstract":"High definition videos contain huge data to be transmitted and received, which is difficult to be sent and stored. In this paper a compression technique based on binary motion vector technique is used to compress HD videos. In which the process of searching for the best matching block for each current block occurs. The proposed technique keeps HD quality with at least Peak Signal to Noise Ratio 62 dB and along with 26% compression ratio on gray scale. The proposed technique is implemented on a Xilinx Vertex 2 2V250fg456 FPGA. The maximum operating speed of the hardware is 63.8 MHz. The FPGA utilization is 12.37% of total CLB slices and 8.61% of total latches.","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125153248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Microprocessor Benchmarks - A Detailed Look at Techniques, Problems and Solutions 微处理器基准-技术，问题和解决方案的详细介绍
2011 21st International Conference on Systems Engineering Pub Date : 2011-08-16 DOI: 10.1109/ICSEng.2011.67
Klaus-Dietrich Kramer, T. Stolze, Alexander Oppelt
{"title":"Microprocessor Benchmarks - A Detailed Look at Techniques, Problems and Solutions","authors":"Klaus-Dietrich Kramer, T. Stolze, Alexander Oppelt","doi":"10.1109/ICSEng.2011.67","DOIUrl":"https://doi.org/10.1109/ICSEng.2011.67","url":null,"abstract":"Benchmarks are used to evaluate performance of various systems. When measuring the performance of Microprocessors, Microcontrollers or Digital Signal Processors, fair benchmarks help defining certain qualities of such systems. There are some parameters, structural characteristics and conditions of the system that possibly distort the benchmarks or even make them more difficult. The presentation illustrates test objects as well as the definition of test conditions of Microprocessor (and MC/DSP) Benchmarking. Beginning with the attempt to classify current benchmark techniques, suggestions on how different units like processor core, IO peripherals and memory (memory structure, memory location, etc.) of Microprocessors, Microcontrollers and DSPs are shown. But it also concentrates on problems that may appear while testing, e.g. regarding to the used compiler (with or without optimization, included libraries, etc.). In order to get comparable and fair results, the presentation focuses on solutions and reveals results of self developed test code - the benchmarks developed at Harz University (HSH -- Benchmarks).","PeriodicalId":387483,"journal":{"name":"2011 21st International Conference on Systems Engineering","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116571521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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