2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)最新文献_第2页

EMI coupling to command lines due to solar array switching strings in spacecraft 航天器太阳能电池阵列开关串对命令行的电磁干扰耦合

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030818

P. Sowjanya, V. Raghavaiah, P. Murthy, R. Renuka, S. Nagesh, M. Thyagaraj, G. Rajan, K. Govinda

引用次数: 3

Fast incremental 3D full-wave analysis for package-board design iterations via eigen-GCR 快速增量三维全波分析封装板设计迭代通过特征- gcr

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030806

G. Chatterjee, A. Das, D. Gope

引用次数: 5

Resonant power supply noise reduction using on-die decoupling capacitors embedded in organic interposer 用嵌在有机中间层内的片上去耦电容器降低谐振电源噪声

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030823

T. Nakura, Masahiro Kano, M. Yoshizawa, Seisei Oyamada, A. Hattori, K. Asada

引用次数: 1

Challenges of using flex cables in high speed serial links 在高速串行链路中使用柔性电缆的挑战

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030820

G. Anand, Vijender Kumar, Mallikarjun Vasa, B. Mutnury

引用次数: 2

Inter layer crosstalk between stripline and metal patch 带状线与金属贴片之间的层间串扰

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030813

Chun-Lin Liao

引用次数: 1

High-speed data transmission system using half mode substrate integrated waveguide 采用半模基片集成波导的高速数据传输系统

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030826

Xi-Wang Yuan, Xiaochun Li, Ning Wang, Xiao-Jian Ma, Yan Shao, J. Mao

引用次数: 7

A super wideband X-complementary split ring resonator structure for power distribution network 配电网超宽带x互补分环谐振器结构

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030817

Ji Zhang, Xiaochun Li, Ning Wang, Na Li, Sheng-jie Guo, J. Mao

引用次数: 0

Eye-height/width prediction from S-Parameters using bounded size training set for ANN 基于有界大小训练集的s参数眼高/眼宽预测

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030804

N. Ambasana, D. Gope, B. Mutnury, G. Anand

{"title":"Eye-height/width prediction from S-Parameters using bounded size training set for ANN","authors":"N. Ambasana, D. Gope, B. Mutnury, G. Anand","doi":"10.1109/EDAPS.2014.7030804","DOIUrl":"https://doi.org/10.1109/EDAPS.2014.7030804","url":null,"abstract":"Validation of high-speed interface performance in a given design space from a Signal Integrity (SI) perspective requires Bit Error Rate (BER) computation. Eye Height (EH) and Eye Width (EW) are used to determine the quality of an interface for a given set of design parameters and frequency of operation. EH, EW and BER estimation requires Time Domain (TD) simulation of complex channel models over billions of bits, which is a time, compute power and memory intensive process. Statistical and optimization techniques such as Design of Experiments (DoE) based on generation of design sets that span the design space optimally exist today. However, it has been shown that DoE based simulations might result in in-accurate sensitivity analysis for highly nonlinear design spaces. Also, the size of a DoE set scales exponentially with the number of design variables. It has been shown in [5] that TD metrics EH and EW, in absence of cross-talk, can be mapped from FD metrics like Return Loss (RL) and Insertion Loss (IL) using Artificial Neural Networks (ANN). The training of the ANNs requires DoE for the existing method. In this paper, an alternative technique to DoE, for generating a training set for ANN is presented, which remains constant over several number of design variables, and scales only in the number of FD metrics used to map to TD metrics and the number of samples in FD. Simulations for SATA 3.0 channel topology with and without cross-talk in TD are presented to quantify the accuracy of the said approach.","PeriodicalId":387223,"journal":{"name":"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124957537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Fast and accurate technique to decompose jitter for very long pattern length waveform 快速和准确的技术分解抖动非常长的模式长度的波形

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030815

J. Kho, Tan Yih Ling

{"title":"Fast and accurate technique to decompose jitter for very long pattern length waveform","authors":"J. Kho, Tan Yih Ling","doi":"10.1109/EDAPS.2014.7030815","DOIUrl":"https://doi.org/10.1109/EDAPS.2014.7030815","url":null,"abstract":"Protocols such as CEI, 10G Ethernet and PCIe Gen3 are requiring very long pattern length stress signals such as PRBS-23 and PRBS-31 to claim compliance and ensure robustness. Unfortunately, there is equipment limitation to directly measure very long pattern signals especially on oscilloscopes due to memory size and signal processing power. Thus, new jitter decomposition algorithms are introduced to measure these long stress patterns through behavioral modeling [1-3]. However, there are accuracy concerns with these new measurement methodologies because of incidences of false results when users attempt to qualify or debug a circuit. This paper will explore the limitations of different jitter decomposition algorithms from major equipment vendors in the industry when measuring very long pattern length waveforms. We will also provide the measurement method and calculations required to obtain the correct jitter decomposition. Correlation of the calculated number against direct measurement using bit error rate tester (BERT) is also done to prove the hypothesis and validate accuracy of the methodology. The findings in this paper are very beneficial in assisting the industry to perform accurate jitter measurements with shorter test time to achieve robust designs as well as prevent precious resources from being spent on investigating false failures. The findings also allow companies to show that their products are tested under stringent conditions that satisfy customer requirements.","PeriodicalId":387223,"journal":{"name":"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125043763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Vref optimization in DDR4 RDIMMs for improved timing margins DDR4 rdimm的Vref优化，以提高时间裕度

2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2014-12-01 DOI: 10.1109/EDAPS.2014.7030810

Saravanan Sethuraman, A. Lingambudi, Kenneth Wright, Abhijit Saurabh, Kyu-Hyoun Kim, D. Becker

{"title":"Vref optimization in DDR4 RDIMMs for improved timing margins","authors":"Saravanan Sethuraman, A. Lingambudi, Kenneth Wright, Abhijit Saurabh, Kyu-Hyoun Kim, D. Becker","doi":"10.1109/EDAPS.2014.7030810","DOIUrl":"https://doi.org/10.1109/EDAPS.2014.7030810","url":null,"abstract":"JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time. With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a novel approach to determine the best VREF settings for a given topology. We will use memory controller built-in-self-test (MCBIST) to get a stressed pattern in place of simple Multi Purpose Register (MPR) data pattern and will be exercised as part of post DRAM training. Data pattern complexity, total training time and accuracy of training are investigated and optimized. Initial training of the DRAM is done with the initial VREF calculated based on driver strength and On Die Termination (ODT) condition. Complexities of different VREF settings are applied on multiple ranks in the same DIMM using the PDA to maximize timing margin and power efficiency. Per-DRAM VREF training has been also performed using PDA to study tradeoff between timing margin and total training time. Our results show significant benefits with respect to PDA vs rank basis Vref training.","PeriodicalId":387223,"journal":{"name":"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116378217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2