2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献

{"title":"A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders","authors":"Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu","doi":"10.1109/ISLPED.2017.8009168","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009168","url":null,"abstract":"In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Experimental results demonstrate that our framework can achieve near-optimal delay vs. power/area Pareto frontier over a wide design space, bridging the gap between architectural and physical designs.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130516920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks","authors":"Arnab Roy, Swagath Venkataramani, Neel Gala, Sanchari Sen, Kamakoti Veezhinathan, A. Raghunathan","doi":"10.1109/ISLPED.2017.8009176","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009176","url":null,"abstract":"Spiking neural networks (SNNs) represent the third generation of neural networks and are expected to enable new classes of machine learning applications. However, evaluating large-scale SNNs (e.g., of the scale of the visual cortex) on power-constrained systems requires significant improvements in computing efficiency. A unique attribute of SNNs is their event-driven nature—information is encoded as a series of spikes, and work is dynamically generated as spikes propagate through the network. Therefore, parallel implementations of SNNs on multi-cores and GPGPUs are severely limited by communication and synchronization overheads. Recent years have seen great interest in deep learning accelerators for non-spiking neural networks, however, these architectures are not well suited to the dynamic, irregular parallelism in SNNs. Prior efforts on specialized SNN hardware utilize spatial architectures, wherein each neuron is allocated a dedicated processing element, and large networks are realized by connecting multiple chips into a system. While suitable for large-scale systems, this approach is not a good match to size or cost constrained mobile devices. We propose PEASE, a Programmable Event-driven processor Architecture for SNN Evaluation. PEASE comprises of Spike Processing Units (SPUs) that are dynamically scheduled to execute computations triggered by a spike. Instructions to the SPUs are dynamically generated by Spike Schedulers (SSs) that utilize event queues to track unprocessed spikes and identify neurons that need to be evaluated. The memory hierarchy in PEASE is fully software managed, and the processing elements are interconnected using a two-tiered bus-ring topology matching the communication characteristics of SNNs. We propose a method to map any given SNN to PEASE such that the workload is balanced across SPUs and SPU clusters, while pipelining across layers of the network to improve performance. We implemented PEASE at the RTL level and synthesized it to IBM 45 technology. Across 6 SNN benchmarks, our 64-SPU configuration of PEASE achieves 7.1×−17.5× and 2.6×−5.8× speedups, respectively, over software implementations on an Intel Xeon E5-2680 CPU and NVIDIA Tesla K40C GPU. The energy reductions over the CPU and GPU are 71×−179× and 198×−467×, respectively.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123923102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design high bandwidth-density, low latency and energy efficient on-chip interconnect","authors":"Yong Wang, Hui Wu","doi":"10.1109/ISLPED.2017.8009171","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009171","url":null,"abstract":"For future high-performance computing chips, on-chip interconnect requires large bandwidth-density, low latency, and high energy-efficiency, which pose significant design challenges. This paper presents a design space exploration of transmission line based on-chip interconnect. First, we conduct an optimization of on-chip transmission lines to minimize the size, channel loss and inter-symbol-interference (ISI), hence to maximize the bandwidth-density. Based on the result, differential coplanar waveguide (CPW) with 55-µm pitch size is chosen as the transmission line topology. Next, channel capacities of channel lengths from 2 to 8 cm are characterized based on time-domain pulse responses. Various equalizers are studied, which are used to increase the ISI-limited channel capacity. To make better use of the large equalized channel capacity, pulse amplitude modulation (PAM) is employed instead of traditional non-return-to-zero (NRZ) signaling. A link budget analysis is then conducted to find the optimal modulation format for each channel. To verify our analyses, several transceivers are designed in 28-nm CMOS technology. An 84-Gb/s PAM-8 transceiver achieves 1.5-Gb/s/μm bandwidth-density over a 4-cm channel. The unrepeated bandwidth-density is 6.1 Gb/s/μm·cm, which is almost 10 times larger compared to prior work.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126289226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Invited paper: Resilient and energy-secure power management","authors":"P. Bose, A. Buyuktosunoglu","doi":"10.1109/ISLPED.2017.8009187","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009187","url":null,"abstract":"We present an industrial design perspective on power management. We focus primarily on server and mainframe class processors. However, recent advances in very low voltage (VLV) research in support of cognitive platforms of the future are also considered. A particular focus is on the special attention that needs to be placed on resilience and energy-secure design principles. The paper discusses how reliability gaps in power management hardware and/or algorithms can expose gaps in security in terms of so-called power attacks. We discuss current industrial practice and describe key challenges that need to be addressed by the research community in this regard. This is designed to be a tutorial-style survey and analysis paper.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127906870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tiguan: Energy-aware collision-free control for large-scale connected vehicles","authors":"Minghua Shen, Guojie Luo","doi":"10.1109/ISLPED.2017.8009184","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009184","url":null,"abstract":"Traditional transportation systems in metropolitan areas always suffer from energy inefficiencies, evidenced by its uncoordinated behaviors such as system capacity and traffic demand change. With the advanced networked sensors are prevalent deployed into the autonomous vehicles, the information of system status and traffic demand can be collected in real-time. These information provides the potential to perform different types of coordination and control for autonomous vehicles in large-scale intelligent transportation systems. In this paper, we design a coordination-based energy-aware control method for large-scale connected vehicles, named Tiguan. Tiguan enables an iterative scheme to compute a practicable solution, which all vehicles are controlled on different trajectory paths of ground traffic network while achieving the close to the optimal performance. Safety is guaranteed by enabling vehicle to autonomously coordinate with other vehicles for a road traffic resource, and thus determine which vehicle needs the resource most. Experimental results show that Tiguan can effectively generate a feasible control solution with collision avoidance, and minimizing the energy consumption.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123369828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An improved clocking methodology for energy efficient low area AES architectures using register renaming","authors":"S. Dhanuskodi, Daniel E. Holcomb","doi":"10.1109/ISLPED.2017.8009193","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009193","url":null,"abstract":"Sub-round implementations of AES have been explored as an area and energy efficient solution to encrypt data in resource constrained applications such as the Internet of Things. Symmetry in AES operations across bytes and words allows the datapath to be scaled down to 8 bits resulting in very compact designs. However, such designs incur an area penalty to store intermediate results or energy penalty to shift data through registers without performing useful computation. We propose a smart clocking scheme and rename registers to minimize data movement and clock loading, and also avoid storing a duplicate copy of the system state. In comparison to the most efficient 8-bit implementation from literature, we save 45% energy per encryption and reduce clock energy by 70% at a reasonable area cost.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126616343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient thermoelectric cooling for mobile devices","authors":"Youngmoon Lee, Eugene Kim, K. Shin","doi":"10.1109/ISLPED.2017.8009199","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009199","url":null,"abstract":"Mobile apps suffer large performance degradation when the underlying processors are throttled to cool down the devices. Fans or heat sinks are not a viable option for mobile devices, thus calling for a new portable cooling solution. Thermoelectric coolers are scalable and controllable cooling devices that can be embedded into mobile devices on the chip surface. This paper presents a thermoelectric cooling solution that enables efficient processor thermal management in mobile devices. Our goal is to minimize performance loss from thermal throttling by efficiently using thermoelectric cooling. Since mobile devices experience large variations in workloads and ambient temperature, our solution adaptively controls cooling power at runtime. Our evaluation on a smartphone using mobile benchmarks demonstrated that the performance loss from the maximum speed is only 1.8% with the TEC compared to 19.2% without the TEC.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132357399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frequency and time domain analysis of power delivery network for monolithic 3D ICs","authors":"Kyungwook Chang, Shidhartha Das, S. Sinha, B. Cline, G. Yeric, S. Lim","doi":"10.1109/ISLPED.2017.8009180","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009180","url":null,"abstract":"As 2D scaling reaches its limit, monolithic 3D IC (M3D) is a leading contender to continue equivalent scaling. Although M3D shows power and performance benefits over 2D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power-supply integrity. In addition, we present frequency- and time-domain analysis of the M3D PDN. We show that the additional resistance in the M3D PDN, while being worse for resistive drops, improves resiliency against current noise showing 35.9% peak impedance reduction during worst-case resonant oscillations.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low-power APUF-based environmental abnormality detection framework","authors":"Hongxiang Gu, T. Xu, M. Potkonjak","doi":"10.1109/ISLPED.2017.8009194","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009194","url":null,"abstract":"Physical unclonable functions (PUFs) take advantage of the effect of process variation on hardware to obtain their unclonability. Traditional PUF design only focuses on the analog signals of circuits. An arbiter PUF, for example, generates responses by racing delay signals. Implementations of such PUFs usually employ large area and power consumption while providing very low throughput. To address this problem, we propose an energy efficient PUF design in such a way that it races analog signals and computes digital logic simultaneously. More importantly, the analog portion of the circuit (racing) shares a large amount of hardware resources with the digital portion of the circuit (computing) by introducing only small overhead in terms of area and power. Our test results on Spartan-6 field-programmable gate array (FPGA) platforms indicate that by combining the two outputs, our design enables much larger PUF output throughput, better randomness and less power consumption compared to traditional PUFs.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123246767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ShiftMask: Dynamic OLED power shifting based on visual acuity for interactive mobile applications","authors":"Han-Yi Lin, P. Hsiu, Tei-Wei Kuo","doi":"10.1109/ISLPED.2017.8009181","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009181","url":null,"abstract":"OLED power management on mobile devices is very challenging due to the dynamic nature of human-screen interaction. This paper presents the design, algorithms, and implementation of a lightweight mobile app called ShiftMask, which allows the user to dynamically shift OLED power to the portion of interest, while dimming the remainder of the screen based on visual acuity. To adapt to the user's focus of attention, we propose efficient algorithms that consider visual fixation in static scenes, as well as changes in focus and screen scrolling. The results of experiments conducted on a commercial smartphone with popular interactive apps demonstrate that ShiftMask can achieve substantial energy savings, while preserving acceptable readability.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121504449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}