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2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX 具有优化体偏置分离的高效节能标准单元存储器的设计与实现方法
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-06-29 DOI: 10.1109/ULIS.2017.7962596
Yusuke Yoshida, K. Usami
{"title":"Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX","authors":"Yusuke Yoshida, K. Usami","doi":"10.1109/ULIS.2017.7962596","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962596","url":null,"abstract":"This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130189488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs 双栅隧道场效应管固有电容的紧凑建模
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962584
A. Farokhnejad, M. Graef, F. Horst, C. Liu, Q. Zhao, B. Iñíguez, F. Lime, A. Kloes
{"title":"Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs","authors":"A. Farokhnejad, M. Graef, F. Horst, C. Liu, Q. Zhao, B. Iñíguez, F. Lime, A. Kloes","doi":"10.1109/ULIS.2017.7962584","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962584","url":null,"abstract":"In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"421 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127316666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
S-shaped gate-all-around MOSFETs for high density design 用于高密度设计的s形栅极全能mosfet
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962566
Ya-Chi Huang, Shui-Jinn Wang, M. Chiang
{"title":"S-shaped gate-all-around MOSFETs for high density design","authors":"Ya-Chi Huang, Shui-Jinn Wang, M. Chiang","doi":"10.1109/ULIS.2017.7962566","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962566","url":null,"abstract":"For maximum utilization of layout area using the vertical gate-all-around (VGAA) MOSFETs, this paper proposes a new S-shaped GAA (SGAA) MOSFET structure for 3D integration. The proposed approach improves the layout density per unit cell to extend Moore's Law without the need of aggressive technology scaling. By adjusting the dimensional parameters in the layout schematic, we can tune the device performance such as drive current easily, thus providing a circuit design flexibility for SoC application. Using the same effective channel width for comparison with others vertical GAA structures, the proposed one gives an advantage in better short-channel effects based on three-dimensional TCAD simulation. In addition, by interlacing SGAAs in a repeated unit cell configuration for high density design, just like multi-finger layout, the area density is increased by 3.3× as compared with the ring-shaped GAA MOSFET.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling and design considerations for negative capacitance field-effect transistors 负电容场效应晶体管的建模和设计考虑
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962577
M. Hoffmann, M. Pešić, S. Slesazeck, U. Schroeder, T. Mikolajick
{"title":"Modeling and design considerations for negative capacitance field-effect transistors","authors":"M. Hoffmann, M. Pešić, S. Slesazeck, U. Schroeder, T. Mikolajick","doi":"10.1109/ULIS.2017.7962577","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962577","url":null,"abstract":"Stabilization of ferroelectric negative capacitance (NC) in a transistor gate stack is a promising pathway towards future low power electronics. However, most modeling efforts of such NCFETs are based on single-domain Landau theory, which is an oversimplification that leads to incorrect predictions and device design. By extending the Landau model to describe more than one domain, it is shown how an internal metal electrode inherently destabilizes NC. Consequently, NCFETs have to be designed without internal metal electrode to function. Furthermore, the use of single-domain Landau theory to model NCFETs with HfO2 based ferroelectrics is critically discussed.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Impact of cryogenic temperature operation on static and low frequency noise behaviors of FD UTBOX nMOSFETs 低温工作对FD UTBOX nmosfet静态和低频噪声行为的影响
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962610
B. Nafaa, B. Crețu, N. Ismail, O. Touayar, E. Simoen
{"title":"Impact of cryogenic temperature operation on static and low frequency noise behaviors of FD UTBOX nMOSFETs","authors":"B. Nafaa, B. Crețu, N. Ismail, O. Touayar, E. Simoen","doi":"10.1109/ULIS.2017.7962610","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962610","url":null,"abstract":"Unusual peaks in the transconductance gm(VGS) characteristics of n-channel UTBOX devices have been evidenced at 10 K and 77 K operation for an applied front gate voltage around 1.1 V while the back gate is grounded. The origin of this behavior was also addressed using additional low frequency noise (LFN) measurements. It is believed that the unusual peak may be related to a tunneling effect through dopants diffused from source/drain extensions in the channel. Low frequency noise spectroscopy around 77 K confirms the presence of boron in the Si film. Back gate biased in accumulation mode at 77 K operation evidenced an additional transconductance peak behavior which may be attributed to the linear kink effect.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127790170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements 反向偏置效应对FDSOI MOSFET射频性能及寄生元件的影响
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962569
B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, J. Raskin
{"title":"Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements","authors":"B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, J. Raskin","doi":"10.1109/ULIS.2017.7962569","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962569","url":null,"abstract":"This work demonstrates that the back-gate terminal of a 28nm FDSOI MOSFET can be used up to several tens of GHz for signal processing. Furthermore, the dependence of the main RF figures-of-merit on the back gate bias are experimentally extracted using a 3-port characterization in the frequency range of 10 MHz – 26.5 GHz. We propose a small-signal equivalent circuit constructed based on 3-port measurements allowing for more complete extraction of parasitic elements comparing to the 2-ports one. The effect of back-gate bias on cut-off frequencies is demonstrated and explained in terms of its influence on the relevant parasitic elements.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121453420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Effects of non-stoichiometry of silicon oxide layers in double barrier structure on high temperature annealing of ultrathin silicon layer 双势垒结构氧化硅层的非化学计量对超薄硅层高温退火的影响
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962573
R. B. Beck, Paweł Korb
{"title":"Effects of non-stoichiometry of silicon oxide layers in double barrier structure on high temperature annealing of ultrathin silicon layer","authors":"R. B. Beck, Paweł Korb","doi":"10.1109/ULIS.2017.7962573","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962573","url":null,"abstract":"Double barrier structure with silicon layer instead of metal can potentially enable variety of intriguing applications of such a structure. The observations so far have pointed out that behavior of such structures during high temperature process may depend on availability of oxygen. It can potentially influence the result of race for silicon atoms between recrystallization and oxidation processes. The aim of this work is to study experimentally influence of excess or deficiency of oxygen (i.e. non-stoichiometric composition) in the barrier oxide layers of this structure (thus having direct contact with ultrathin silicon layer) during high temperature processes in controlled ambient atmosphere.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"314 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115353339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hall-effect mobility for a selection of natural and synthetic 2D semiconductor crystals 选择天然和合成二维半导体晶体的霍尔效应迁移率
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962592
S. Monaghan, F. Gity, R. Duffy, G. Mirabelli, Melissa M. McCarthy, K. Cherkaoui, I. Povey, R. Nagle, P. Hurley, J. Lindemuth, E. Napolitani
{"title":"Hall-effect mobility for a selection of natural and synthetic 2D semiconductor crystals","authors":"S. Monaghan, F. Gity, R. Duffy, G. Mirabelli, Melissa M. McCarthy, K. Cherkaoui, I. Povey, R. Nagle, P. Hurley, J. Lindemuth, E. Napolitani","doi":"10.1109/ULIS.2017.7962592","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962592","url":null,"abstract":"We present a DC-AC Hall-effect analysis on transition-metal-dichalcogenides comprising natural crystals of molybdenum disulfide and tungsten diselenide; and synthetic crystals of hafnium diselenide, molybdenum ditelluride, molybdenum diselenide and niobium-doped molybdenum disulfide. We observe a wide range of Hall mobility and carrier concentration values with either a net electron or hole carrier type. The synthetic niobium-doped molybdenum disulfide crystal exhibits a net hole carrier type and a carrier concentration approximately two orders of magnitude higher than a non-intentionally doped natural molybdenum disulfide crystal, with an equivalent reduction in Hall mobility. This synthetic niobium-doped molybdenum disulfide crystal also shows a significantly reduced resistivity when compared to the other crystals. Secondary ion mass spectrometry shows higher counts of niobium in the intentionally-doped synthetic niobium-molybdenum disulfide crystal, in addition to various other high contamination counts in both the natural and synthetic molybdenum disulfide crystals, correlating well with the significant range of high resistivity observed. Compared to silicon, the resistivity in these contaminated TMD materials reduces less rapidly with increasing equivalent carrier concentration levels, and the resistivity is higher in magnitude by a factor of approximately 4–10 when compared to silicon, which in turn reduces the achievable Hall mobility by at least a similar factor. It is therefore suggested that more controlled growth methods of TMD materials which lead to significantly reduced contamination elements and levels, with improved stoichiometry, could potentially provide a significant increase in Hall mobility assuming no change in carrier properties.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122671644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Is there a kink effect in FDSOI MOSFETs? FDSOI mosfet是否存在扭结效应?
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962564
H. J. Park, M. Bawedin, K. Sasaki, J. Martino, S. Cristoloveanu
{"title":"Is there a kink effect in FDSOI MOSFETs?","authors":"H. J. Park, M. Bawedin, K. Sasaki, J. Martino, S. Cristoloveanu","doi":"10.1109/ULIS.2017.7962564","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962564","url":null,"abstract":"Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the potential was probed to evidence the role of majority carrier excess during the kink effect onset.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Characterization of semiconductor structures using scanning microwave microscopy technique 用扫描微波显微镜技术表征半导体结构
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-03 DOI: 10.1109/ULIS.2017.7962561
Bendehiba Abadlia Bagdad, F. Gámiz
{"title":"Characterization of semiconductor structures using scanning microwave microscopy technique","authors":"Bendehiba Abadlia Bagdad, F. Gámiz","doi":"10.1109/ULIS.2017.7962561","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962561","url":null,"abstract":"In this work, we have developed a near field scanning microwave microscopy method and applied it to study semiconductor samples. To do so, we have used a commercial Atomic Force Microscope (NT-NMDT Integra) to which we have coupled a half wavelength micro-strip line resonator and an Agilent N5242A PNA-X Network Analyzer. The AFM tip is connected at the edge of the microstrip which is connected to the PNA. The reflection coefficient S11 is measured as the tip is scanned, at some distance and without contacting it, on the device under test. The variations of the S11 parameter are related to the topographical and dielectric properties of the material under the tip.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114518977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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