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2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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The mystery of the Z2-FET 1T-DRAM memory Z2-FET 1T-DRAM内存的奥秘
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-01 DOI: 10.1109/ULIS.2017.7962598
M. Bawedin, H. El Dirani, K. Lee, M. Parihar, J. Lacord, S. Martinie, C. Le Royer, J. Barbe, X. Mescot, P. Fonteneau, P. Galy, F. Gámiz, C. Navarro, B. Cheng, A. Asenov, Y. Taur, S. Cristoloveanu
{"title":"The mystery of the Z2-FET 1T-DRAM memory","authors":"M. Bawedin, H. El Dirani, K. Lee, M. Parihar, J. Lacord, S. Martinie, C. Le Royer, J. Barbe, X. Mescot, P. Fonteneau, P. Galy, F. Gámiz, C. Navarro, B. Cheng, A. Asenov, Y. Taur, S. Cristoloveanu","doi":"10.1109/ULIS.2017.7962598","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962598","url":null,"abstract":"We review the operation mechanisms of the Z2-FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132685174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Properties of III–V nanowires: MOSFETs and TunnelFETs III-V型纳米线的特性:mosfet和tunnelfet
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-01 DOI: 10.1109/ULIS.2017.7962611
L. Wernersson
{"title":"Properties of III–V nanowires: MOSFETs and TunnelFETs","authors":"L. Wernersson","doi":"10.1109/ULIS.2017.7962611","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962611","url":null,"abstract":"This paper describes the properties and performance status of vertical III–V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130054309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing 通过反偏置提高SOI纳米线nmosfet自级联编码的模拟性能
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-01 DOI: 10.1109/ULIS.2017.7962607
R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot
{"title":"Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing","authors":"R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot","doi":"10.1109/ULIS.2017.7962607","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962607","url":null,"abstract":"In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134503082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluation of ONO compatibility with high-k metal gate stacks for future embedded flash products 评估ONO与未来嵌入式闪存产品的高k金属栅极堆栈的兼容性
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-01 DOI: 10.1109/ULIS.2017.7962616
A. Dobri, Dann Morillon, S. Jeannot, F. Piazza, C. Jahan, A. Toffoli, L. Perniola, F. Balestra
{"title":"Evaluation of ONO compatibility with high-k metal gate stacks for future embedded flash products","authors":"A. Dobri, Dann Morillon, S. Jeannot, F. Piazza, C. Jahan, A. Toffoli, L. Perniola, F. Balestra","doi":"10.1109/ULIS.2017.7962616","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962616","url":null,"abstract":"Embedded flash memories having high-k metal gate-based logic devices will require modifications to the flash cells in order to remain economically feasible. One potential integration scheme is to keep the traditional ONO layer as the flash cell's inter-gate dielectric and replace its poly-Si control gate with the same high-k metal gate stack used for the logic devices. Preliminary electrical tests show that an HfSiON/TiN/a-Si gate stack does not significantly impact the EOT or leakage properties of the ONO layer. This stack is more robust than the traditional ONO with a poly-Si gate.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Strain-induced increase of electron mobility in ultra-thin InGaAs-OI MOS transistors 超薄InGaAs-OI MOS晶体管中应变诱导的电子迁移率增加
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2017-04-01 DOI: 10.1109/ULIS.2017.7962583
S. Krivec, M. Poljak, T. Suligoj
{"title":"Strain-induced increase of electron mobility in ultra-thin InGaAs-OI MOS transistors","authors":"S. Krivec, M. Poljak, T. Suligoj","doi":"10.1109/ULIS.2017.7962583","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962583","url":null,"abstract":"The impact of strain on the electron mobility is investigated in ultra-thin InGaAs-OI channels by combining tight-binding bandstructure simulations, self-consistent Schrodinger-Poisson, and mobility simulations including all relevant scattering mechanisms. Our model shows that strain induced mobility improvement increases with body thickness downscaling, up to 164% in 4 nm-thick InGaAs channels in strong inversion.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129119698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Experimental comparison between relaxed and strained Ge pFinFETs 松弛与应变Ge pfinet的实验比较
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 1900-01-01 DOI: 10.1109/ULIS.2017.7962576
A. Oliveira, P. Agopian, J. Martino, E. Simoen, J. Mitard, L. Witters, N. Collaert, C. Claeys
{"title":"Experimental comparison between relaxed and strained Ge pFinFETs","authors":"A. Oliveira, P. Agopian, J. Martino, E. Simoen, J. Mitard, L. Witters, N. Collaert, C. Claeys","doi":"10.1109/ULIS.2017.7962576","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962576","url":null,"abstract":"The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low temperature performance of proton irradiated strained SOI FinFET 质子辐照应变SOI FinFET的低温性能
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 1900-01-01 DOI: 10.1109/ULIS.2017.7962601
L. Caparroz, C. Bordallo, J. Martino, E. Simoen, C. Claeys, P. Agopian
{"title":"Low temperature performance of proton irradiated strained SOI FinFET","authors":"L. Caparroz, C. Bordallo, J. Martino, E. Simoen, C. Claeys, P. Agopian","doi":"10.1109/ULIS.2017.7962601","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962601","url":null,"abstract":"This paper studies for the first time the low temperature characteristics of strained SOI FinFETs submitted to proton irradiation. Both types of transistors, nMOS and pMOS, were analyzed from room temperature down to 100K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA and the intrinsic gain voltage (AV). The effects of strain techniques are also studied. The p-channel devices showed a greater immunity to radiation when looking at their digital parameters while nFinFETs had a better response to proton radiation from an analog parameters point of view.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114268813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Feasibility demonstration of new e-NVM cells suitable for integration at 28nm 适用于28nm集成的新型e-NVM电池的可行性论证
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 1900-01-01 DOI: 10.1109/ULIS.2017.7962599
S. Kalem, S. Tekin, R. Roelofs
{"title":"Feasibility demonstration of new e-NVM cells suitable for integration at 28nm","authors":"S. Kalem, S. Tekin, R. Roelofs","doi":"10.1109/ULIS.2017.7962599","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962599","url":null,"abstract":"Memory cell selection for 28 nm and beyond and its integration into new eNVM technology have been investigated through atomic layer deposition (ALD) HfO2 resistive memory devices. Both amorphous and crystalline HfO2 layers exhibit promising switching characteristics. It was shown that more than 3 times less power is required to activate the memory device fabricated using the amorphous layer. The forming voltages for both of the memory cell are greater than 10 Volt relative to layer thickness of 50 nm. As an alternative potential resistive memory element, SiOx layer formed on n and p type Si wafers exhibited interesting forming features.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of the transistor efficiency of gas phase Zn diffusion In0.53Ga0.47As nTFETs at different temperatures 不同温度下气相Zn扩散In0.53Ga0.47As ntfet晶体管效率分析
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 1900-01-01 DOI: 10.1109/ULIS.2017.7962614
C. Bordallo, J. Martino, P. Agopian, A. Alian, Y. Mols, R. Rooyackers, A. Vandooren, A. Verhulst, E. Simoen, C. Claeys, N. Collaert
{"title":"Analysis of the transistor efficiency of gas phase Zn diffusion In0.53Ga0.47As nTFETs at different temperatures","authors":"C. Bordallo, J. Martino, P. Agopian, A. Alian, Y. Mols, R. Rooyackers, A. Vandooren, A. Verhulst, E. Simoen, C. Claeys, N. Collaert","doi":"10.1109/ULIS.2017.7962614","DOIUrl":"https://doi.org/10.1109/ULIS.2017.7962614","url":null,"abstract":"In this work, the influence of the temperature and the different equivalent oxide thickness (EOT) of In0.53Ga0.47As nTFETs fabricated with gas phase Zn diffusion is analyzed. The different devices have in their gates stacks 3 nm of HfO2 (with an EOT of 1 nm) or 2 nm of HfO2 (with an EOT of 0.8 nm). The use of an EOT of 0.8 nm increases the band-to-band tunneling generation and also improves the subthreshold region characteristics, presenting a sub 60 mV/dec minimum subthreshold swing (56 mV/dec) at room temperature, resulting in better efficiency in weak conduction. Considering the temperature influence, the on-state current is less affected than the off-state current due to the band-to-band tunneling mechanism. In the subthreshold region the temperature decrease, which strongly reduces the off-state current, allows the band-to-band tunneling current to be more dominant, resulting in a better subthreshold swing and, consequently, a better transistor efficiency in the weak conduction regime. The opposite behavior occurs when heating the devices, reducing the influence of the band-to-band tunneling in the subthreshold region, degrading both the subthreshold swing and transistor efficiency in the weak conduction regime. In the strong conduction regime, the transistor follows the transconductance tendency, increasing for higher temperatures.","PeriodicalId":383716,"journal":{"name":"2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121555310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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