2016 IEEE-NPSS Real Time Conference (RT)最新文献_第8页

Fuzzy-PID based heating control system 基于模糊pid的加热控制系统

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543084

S. Dong, F. Jiang, Jie Chen, Hongfei Zhang, Jian Wang

引用次数: 6

New LLRF control system at LNL LNL的新型LLRF控制系统

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543105

D. Bortolato, S. Pavinato, D. Pedretti, M. Betti, F. Gelain, D. Marcato, M. Bellato, R. Isocrate, Matteo Bertocco

{"title":"New LLRF control system at LNL","authors":"D. Bortolato, S. Pavinato, D. Pedretti, M. Betti, F. Gelain, D. Marcato, M. Bellato, R. Isocrate, Matteo Bertocco","doi":"10.1109/RTC.2016.7543105","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543105","url":null,"abstract":"The Low-level Radio Frequency (LLRF) control system for linear accelerator at Legnaro National Laboratories (LNL) of INFN is being upgraded by a new digital Radio Frequency (RF) controller. This controller is critical to keep phase, amplitude and frequency stability of the RF field in Quarter Wave Resonator (QWR) cavities of the linear accelerator. These cavities work in superconducting condition. The resonance frequency of low beta cavities is 80 MHz, while medium and high beta cavities resonate at 160 MHz. Each RF controller can control at the same time eight different cavities. The RF signals picked-up from the cavities are sampled by RF ADCs. The digitized signals are fed into a field programmable gate array (FPGA) which implements the control loop. The signals processed by the FPGA are in-phase/quadrature modulated and sent to power amplifiers and hence to the cavities. The main feature of the new control system is an all-digital control loop that originates from direct sampling of the antenna RF signal. In-phase and quadrature components are obtained by a suitable choice of the undersampling frequency, while control of the field and phase in the cavity is based on a digital Complex Phase Modulator (CPM). This paper presents the FPGA firmware, the acquisition techniques and the performances of the new RF controller.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127962746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

TaskRouter: A newly designed online data processing framework TaskRouter:一个新设计的在线数据处理框架

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543088

M. Gu, K. Zhu, Fei Li, W. Shen

引用次数: 1

Analog data acquisition and processing FPGA-based solutions integrated in areaDetector using FlexRIO technology 模拟数据采集和处理基于fpga的解决方案集成在使用FlexRIO技术的areaDetector

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543177

Ricardo Herrero, A. Carpeño, S. Esquembri, M. Ruiz, E. Barrera

{"title":"Analog data acquisition and processing FPGA-based solutions integrated in areaDetector using FlexRIO technology","authors":"Ricardo Herrero, A. Carpeño, S. Esquembri, M. Ruiz, E. Barrera","doi":"10.1109/RTC.2016.7543177","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543177","url":null,"abstract":"Analog data acquisition used in diagnostics and control of large physics experiments require high sampling rates and real-time functionalities. Field Programmable Gate Array (FPGA) devices allow efficient implementation of such solutions. Currently, large scientific facilities are using middleware platforms to simplify systems integration. EPICS (Experimental Physics and Industrial Control System) is one of the most extended middleware for this purpose. Heterogeneous hardware integration in these middleware is a complex task, and different approaches attempt to standardize. One of these approaches is areaDetector. An open source module for EPICS that is mainly used for image acquisition. areaDetector simplifies integration of heterogeneous image systems, has also been used with some analog signals like quadEM. This paper presents the integration of an acquisition and processing solution in a PXIe platform using FlexRIO technology via a hardware model that solves acquisition and processing in a FPGA and a software model implemented in C++ with the IRIO library (open source solution for RIO devices in the Linux environment) to get to EPICS through areaDetector with analog data.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116453516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High speed continuous DAQ system for readout of the ALICE SAMPA ASIC 用于ALICE SAMPA ASIC读出的高速连续数据采集系统

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543104

G. Tambave, A. Velure

引用次数: 4

3D photon impact determination in monolithic based PET detectors using FPGA processing 基于FPGA处理的单片PET探测器三维光子冲击测定

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543141

A. Aguilar, M. Galasso, J. Barberá, C. Correcher, A. Fabbri, L. Hernández, Antonio J. González, J. Benlloch

{"title":"3D photon impact determination in monolithic based PET detectors using FPGA processing","authors":"A. Aguilar, M. Galasso, J. Barberá, C. Correcher, A. Fabbri, L. Hernández, Antonio J. González, J. Benlloch","doi":"10.1109/RTC.2016.7543141","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543141","url":null,"abstract":"This work shows the implementation of novel methods to accurately determine the gamma ray impact position within monolithic scintillation crystals in PET systems. These methods have been implemented in an FPGA (Kintex 7) installed on each ADC board of the data acquisition system (DAQ) of the brain PET insert named MindView to provide the 511 keV photon impinging coordinates in real time. Two different methods have been compared: the commonly used Center of Gravity (CoG) approach and an alternative method named RTP (Raise To the Power) in combination with an estimation of the gamma photons DOI (depth of interaction). The DOI is estimated through the ratio of the energy to the peak maximum intensity of each light distribution. Despite CoG has been implemented with DSPs, performance has been improved with the RTP approach LUT-based, reducing the processing time from 1μ to 640 ns. The achieved time performance including the current development has been measured to be around 640 ns, ensuring the processing of all detected events at high data rates. The obtained results using the FPGA implementation have been compared to data processed off-line after directly transferred the whole raw data to a PC workstation. Here, we compared detector image quality in terms of spatial resolution and DOI capabilities without observing any difference.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122157451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A 3.9 ps RMS resolution time-to-digital converter using dual-sampling method on Kintex UltraScale FPGA 基于Kintex UltraScale FPGA的3.9 ps RMS双采样分辨率时间-数字转换器

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543081

Chong Liu, Yonggang Wang, P. Kuang, Deng Li, Xinyi Cheng

{"title":"A 3.9 ps RMS resolution time-to-digital converter using dual-sampling method on Kintex UltraScale FPGA","authors":"Chong Liu, Yonggang Wang, P. Kuang, Deng Li, Xinyi Cheng","doi":"10.1109/RTC.2016.7543081","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543081","url":null,"abstract":"The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124951512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

The BGO system for real time beam background monitoring in BEAST II BEAST II中用于实时波束背景监测的BGO系统

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543138

J. Shiu, M. Wang, Y. Chen, J. Liau, J. Lin, F. Lin, S. Koirala, K. Lin, K. Chu

引用次数: 0

Data processing for EAST remote participation 用于EAST远程参与的数据处理

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543126

Xiaoyang Sun, Feng Wang, Yong Wang, Shi Li

引用次数: 0

Distributed and parallel real-time control system equipped FPGA-Zynq and EPICS middleware 采用FPGA-Zynq和EPICS中间件的分布式并行实时控制系统

2016 IEEE-NPSS Real Time Conference (RT) Pub Date : 2016-06-06 DOI: 10.1109/RTC.2016.7543117

Sangil Lee, C. Son, H. Jang

{"title":"Distributed and parallel real-time control system equipped FPGA-Zynq and EPICS middleware","authors":"Sangil Lee, C. Son, H. Jang","doi":"10.1109/RTC.2016.7543117","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543117","url":null,"abstract":"Zynq series of Xilinx FPGA chips are divided into Processing System (PS) and Programmable Logic (PL), as a kind of SoC (System on Chip). PS with the dual-core ARM CortexA9 processor is performing the high-level control logic at run-time on Linux operating system. PL with the low-level Field Programmable Gate Array (FPGA) built on high-performance, low-power, and high-k metal gate process technology is connecting with a lot of I/O peripherals for real-time control system. EPICS (Experimental Physics and Industrial Control System) is a set of open-source-based software tools which supports for the Ethernet-based middleware layer. In order to configure the environment of the distributed control system, EPICS middleware is equipped on the Linux operating system of the Zynq PS. In addition, a lot of digital logic gates of the Zynq PL of FPGA-Zynq evaluation board (ZedBoard) are connected with I/O pins of the daughter board via FPGA Mezzanine Connector (FMC) of ZedBoard. An interface between the Zynq PS and PL is interconnected with AMBA4 AXI. For the organic connection both the PS and PL, it also used the Linux device driver for AXI interface. This paper describes the content and configuration of the distributed and parallel real-time control system applying FPGA-Zynq and EPICS middleware.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121193966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7