基于Kintex UltraScale FPGA的3.9 ps RMS双采样分辨率时间-数字转换器

Chong Liu, Yonggang Wang, P. Kuang, Deng Li, Xinyi Cheng
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引用次数: 6

摘要

基于分接延迟线(TDL)式现场可编程门阵列(FPGA)的时间-数字转换器(TDC)的原理要求更细的延迟粒度以获得更高的时间分辨率。给定FPGA中由进位链构成的抽头延迟线,需要找到进一步细分固有延迟元素的解决方案,以便TDC可以实现超过其单元延迟的时间分辨率。本文在探索了Xilinx Kintex UltraScale FPGA中可用的逻辑资源后,提出了一种双采样方法,对TDL状态进行两次采样。新方法的效果相当于将延迟线上的抽头数量增加一倍,因此在时间分辨率上应该有显着的改善。在Kintex UltraScale FPGA上实现了两个TDC通道,并对新方法的有效性进行了研究。在0 ~ 440 ns的固定时间间隔内,双采样法测得的平均时间分辨率为3.9 ps,单采样法测得的平均时间分辨率为5.8 ps。此外,TDC设计保持了我们之前设计的多通道能力和高测量吞吐量的优点。TDC的每一部分,包括双采样、码转换和在线校准,都可以在500mhz时钟频率下运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 3.9 ps RMS resolution time-to-digital converter using dual-sampling method on Kintex UltraScale FPGA
The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.
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