2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)最新文献

{"title":"Virtualization of Reconfigurable Mixed-Criticality Systems","authors":"Cornelia Wulf, Najdet Charaf, Diana Göhringer","doi":"10.1109/FPL57034.2022.00020","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00020","url":null,"abstract":"The increasing complexity of reconfigurable embedded systems often requires the integration of multiple applications with potentially different levels of criticality on the same hardware platform. As the deployment scales, there is a need for resource management, isolation, and performance that makes FPGA virtualization techniques a key consideration. FPGA virtualization enables multiple guest operating systems to run with different requirements, such as real-time, safety, or security. Most state-of-the-art systems incorporate mechanisms to strictly isolate subsystems in spatial respect at the expense of lower resource utilization. In this work, we present L4ReC, a microkernel-based virtualization layer that enables the sharing of reconfigurable resources among multiple virtual machines. The mapping and scheduling strategy for hardware threads considers not only deadlines, but also the real-time levels of guest operating systems. A POSIX thread-based interface facilitates the access to hardware accelerators. Compared with an existing scheduler for hardware threads, the average utilization factor - indicating the FPGA resource usage - is 1,9 times higher when threads are mapped and scheduled with L4ReC. Deadline misses are reduced by 3%.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121620975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware","authors":"Donal Campbell, C. Rafferty, A. Khalid, Máire O’Neill","doi":"10.1109/FPL57034.2022.00079","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00079","url":null,"abstract":"This research investigates efficient architectures for the implementation of the CRYSTALS-Dilithium post-quantum digital signature scheme on reconfigurable hardware, in terms of speed, memory usage, power consumption and resource utilisation. Post quantum digital signature schemes involve a significant computational effort, making efficient hardware accelerators an important contributor to future adoption of schemes. This is work in progress, comprising the establishment of a comprehensive test environment for operational profiling, and the investigation of the use of novel architectures to achieve optimal performance.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115349914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices","authors":"Andrew Boutros, E. Nurvitadhi, Vaughn Betz","doi":"10.1109/FPL57034.2022.00072","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00072","url":null,"abstract":"With the continued growth in field-programmable gate array (FPGA) capacity and their incorporation into new environments such as datacenters, we have witnessed the introduction of a new class of reconfigurable acceleration devices (RADs) that go beyond conventional FPGA architectures. These devices combine a reconfigurable fabric with coarse-grained domain-specialized accelerator blocks all connected via a high-performance packet-switched network-on-chip (NoC) for efficient system-wide communication. However, we lack the tools necessary to efficiently explore the huge design space for RADs, study the complex interactions between their different components and evaluate various combinations of design choices. In this work, we develop RAD-Sim, a cycle-level architecture simulator that allows rapid application-driven exploration of the design space of novel RADs. To showcase the capabilities of RAD-Sim, we map and simulate a state-of-the-art deep learning (DL) inference overlay on a RAD instance incorporating an FPGA fabric and a complex of hard matrix-vector multiplication engines, communicating over a system-wide NoC. Through this example, we show how RAD-Sim can help architects quantify the effect of changing specific architecture parameters on end-to-end application performance.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124809525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations","authors":"Ruizhe Zhao, Jianyi Cheng, W. Luk, G. Constantinides","doi":"10.1109/FPL57034.2022.00044","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00044","url":null,"abstract":"Polyhedral optimization can parallelize nested affine loops for high-level synthesis (HLS), but polyhedral tools are HLS-agnostic and can worsen performance. Moreover, HLS tools require user directives which can produce unreadable polyhedral-transformed code. To address these two challenges, we present POLSCA, a compiler framework that improves polyhedral HLS workflow by automatic code transformation. POLSCA decomposes a design before polyhedral optimization to balance code complexity and parallelism, while revising memory interfaces of polyhedral-transformed code to make partitioning explicit for HLS tools; it enables designs to benefit more easily from polyhedral optimization. Experiments on Polybench/C show that POLSCA designs are 1.5 times faster on average compared with baseline designs generated directly from applying HLS on C code.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA","authors":"Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen","doi":"10.1109/FPL57034.2022.00017","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00017","url":null,"abstract":"Dense and accurate optical flow estimation is an important requirement for dynamic scene perception in autonomous systems. However, most of the existing FPGA accelerators are based on classic methods, which cannot deal with large displacements of moving objects in ultra-fast scenes. In this paper, we present Ultra-Flow, an ultra-fast pipelined architecture for efficient optical flow estimation and refinement. Ultra-Flow utilizes binary neural networks to generate the robust feature map, on which hierarchical matching is directly performed. Therefore, multiple usages of neural networks at hierarchical levels can be avoided to achieve hardware efficiency in Ultra-Flow. Optimizations, including local flow regularization and enhanced matching, are further used to improve the throughput and refine the optical flow to obtain higher accuracy. Evaluation results show that, compared to state-of-the-art FPGA accelerators, Ultra-Flow achieves leading accuracy in the Middlebury sequences at ultra-fast processing speed up to 687.92 frames/s for 640 × 480 pixel images.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121139646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems","authors":"Ahmed Kamaleldin, Diana Göhringer","doi":"10.1109/FPL57034.2022.00053","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00053","url":null,"abstract":"Multi/manycore Systems-on-Chip are increasingly adopted for heterogeneous systems, providing a high degree of computing scalability and energy efficiency. However, the steady increase in heterogeneous tiles number leads to an expansion in resource usage and design cost. Therefore, reusability and modularity of the tile architecture to support different types of compute or memory units are key elements to reduce resource usage. Meanwhile, with the proliferation of RISC-V instruction set architecture, the modularity and reusability of compute tiles have been increased. In this work, we present a modular and reusable memory/accelerator tile architecture that supports two modes of operations as a memory or an accelerator tile. The proposed tile architecture is suitable to be integrated into a NoC based manycore architecture along with RISC-V based compute tiles. The hybrid tile features a shared non-coherent scratchpad memory that can be accessed directly by RISC-V compute tiles through NoC or by the local hardware accelerator logic inside the tile. Tile mode configuration and data transfer over the NoC are managed through control messages issued by RISC-V compute tiles based on running application requirements. Moreover, the proposed tile supports the flexibility to change the local hardware accelerator functionality at run-time using dynamic and partial reconfiguration. For evaluation, two manycore configurations are developed including 4 and 8 RISC-V compute tiles with 4 cores per tile. Several use cases based on signal processing kernels and hardware accelerators are used for performance evaluation in terms of memory transfer latency and computing time for two manycore configurations. Maximum data transfer throughput of 500 MB/s is achieved between the proposed hybrid tile and a single RISC-V compute tile. The proposed tile architecture is implemented and evaluated on a Xilinx Virtex Ultrascale+ FPGA.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116510640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs","authors":"T. Miyoshi, K. Koike, Shinichi Morisaka, H. Shiomi, Kazuhisa Ogawa, Y. Tabuchi, M. Negoro","doi":"10.1109/FPL57034.2022.00089","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00089","url":null,"abstract":"This demonstration shows a Quantum-Classical interface (QC-IF) for quantum computing implemented on multiple FPGAs. Quantum computers need a controller to transmit/receive microwave to/from quantum devices. In order to explore various quantum devices, the controller requires flexibility to transmit/receive various wave shapes. In addition to that, scalability is also required for large-scale quantum computers. FPGAs are attractive platforms; however, some challenges exist in implementing QC-IF on FPGAs in terms of required specifications from physics, such as treating data and realizing scalability. This work demonstrates an implementation of QC-IF on FPGA with high bandwidth memory to treat large-volume data in high throughput. Furthermore, the IEEE1588-like clock synchronization mechanism is implemented to make multiple FPGAs synchronized.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122143558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tunable Fine-grained Clock Phase-shifting for FPGAs","authors":"Bardia Babaei, Dirk Koch","doi":"10.1109/FPL57034.2022.00064","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00064","url":null,"abstract":"High-resolution phase shifters have important practical applications in PET scanners, time-to-digital converters, and characterizing of the FPGA resources. This paper presents a fine-grained clock phase-shifting technique based on the FPGAs' clock managers' dynamic phase shifting capability that is commonly available on all recent FPGAs. Our method allows adjusting the phase shift resolution in the sub-picosecond range independent of the operating frequency. Experiments carried out on a Xilinx UltraScale+ FPGA show that phase-shifting resolution can be adjusted down to 88 f s in these devices. To verify the performance of this method, we have deployed it in a delay characterization circuit to measure the FPGA's resources delays. The experiments show that we can measure path delays below 1 ns which is impossible in conventional frequency sweep-based methods and we reach a much finer time resolution.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133758366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Auto-Tuning of Raw Filters for FPGAs","authors":"Tobias Hahn, S. Wildermann, Jürgen Teich","doi":"10.1109/FPL57034.2022.00036","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00036","url":null,"abstract":"Many Big Data applications include the processing of data streams on semi-structured data formats such as JSON. A disadvantage of these formats, however, is that applications may require a significant portion of their processing time to unselectively parse all data. As a remedy, so-called raw filters have been introduced in the past, aiming to reduce the data load before the costly parsing stage. Since filtering unparsed data can also become very costly, raw filters can be designed to filter data approximately, in the sense that they allow false positives to occur, in order to be implemented efficiently. While previously proposed CPU-based solutions are restricted to just string filtering, FPGA approaches have recently been proposed with much more expressive raw filters, allowing also to capture numbers and structural relationships. Yet, as a consequence of the variety of filter possibilities as well as the limited amount of resources available on FPGAs, the selection of optimal filters before their deployment has been identified as a complex problem resulting in the potential need to select less expressive filters in order to consume fewer resources. Many Big Data applications (e.g., stream processing) operate on incoming real-time data over long, potentially unlimited time periods. As a consequence, the conditions for which such a filter is optimized can change over time after its deployment. In this realm, this paper presents a new methodology which automatically adapts the hardware accelerator for raw filtering by means of dynamic hardware reconfiguration. Data is sampled on-the-fly during operation and used by an optimizer-in-the-loop to select and generate a raw filter with optimized selectivity for these data samples. As the optimizer has to take into account the resource costs of the hardware accelerator, we introduce models to estimate the resource costs in order to avoid performing a full synthesis. The filter selection problem can thus be solved within a few minutes with results close to the accurate resource cost estimation. If the selectivity of a query changes over time, such as seasonal differences in the analysis of IoT data, the system can auto-tune its filter to adapt to the situation. Depending on the query and the variability of inherent data changes, significant improvements in the amount of filtered data are presented, resulting in a significant parsing speedup in comparison to a state-of-the-art non-adaptive approach.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132555250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feature dimensionality in CNN acceleration for high-throughput network intrusion detection","authors":"Laurens Le Jeune, T. Goedemé, N. Mentens","doi":"10.1109/FPL57034.2022.00062","DOIUrl":"https://doi.org/10.1109/FPL57034.2022.00062","url":null,"abstract":"With the ever increasing need for better cybersecurity, and due to the continuous growth of network traffic bandwidths, there is a continuous pursuit of faster and smarter network intrusion detection systems. Neural network-based solutions on FPGAs are very effective in detecting different types of attacks, but have problems with analyzing network traffic online at line speed. One important bottleneck that limits the throughput in raw traffic-based existing systems, is the input shape of the features that are extracted from the raw data. In this work, we propose new methods for extracting and representing features based on raw network traffic in online network intrusion detection systems. We show that feature dimensionality has a significant influence on the classification accuracy and the throughput. Our experiments are based on FPGA-based neural networks accelerated through FINN. We compare three newly proposed input shapes to the traditional 2D-based approach, and we show that two of the presented techniques greatly surpass the state-of-the-art with regards to accuracy and throughput. Our best architecture reaches a maximum bandwidth of 23.09 Gbps, while maintaining over 99% accuracy on both the UNSW-NB15 and CICIDS2017 datasets.","PeriodicalId":380116,"journal":{"name":"2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129516062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}