A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems

Abstract

Multi/manycore Systems-on-Chip are increasingly adopted for heterogeneous systems, providing a high degree of computing scalability and energy efficiency. However, the steady increase in heterogeneous tiles number leads to an expansion in resource usage and design cost. Therefore, reusability and modularity of the tile architecture to support different types of compute or memory units are key elements to reduce resource usage. Meanwhile, with the proliferation of RISC-V instruction set architecture, the modularity and reusability of compute tiles have been increased. In this work, we present a modular and reusable memory/accelerator tile architecture that supports two modes of operations as a memory or an accelerator tile. The proposed tile architecture is suitable to be integrated into a NoC based manycore architecture along with RISC-V based compute tiles. The hybrid tile features a shared non-coherent scratchpad memory that can be accessed directly by RISC-V compute tiles through NoC or by the local hardware accelerator logic inside the tile. Tile mode configuration and data transfer over the NoC are managed through control messages issued by RISC-V compute tiles based on running application requirements. Moreover, the proposed tile supports the flexibility to change the local hardware accelerator functionality at run-time using dynamic and partial reconfiguration. For evaluation, two manycore configurations are developed including 4 and 8 RISC-V compute tiles with 4 cores per tile. Several use cases based on signal processing kernels and hardware accelerators are used for performance evaluation in terms of memory transfer latency and computing time for two manycore configurations. Maximum data transfer throughput of 500 MB/s is achieved between the proposed hybrid tile and a single RISC-V compute tile. The proposed tile architecture is implemented and evaluated on a Xilinx Virtex Ultrascale+ FPGA.