Tunable Fine-grained Clock Phase-shifting for FPGAs

Abstract

High-resolution phase shifters have important practical applications in PET scanners, time-to-digital converters, and characterizing of the FPGA resources. This paper presents a fine-grained clock phase-shifting technique based on the FPGAs' clock managers' dynamic phase shifting capability that is commonly available on all recent FPGAs. Our method allows adjusting the phase shift resolution in the sub-picosecond range independent of the operating frequency. Experiments carried out on a Xilinx UltraScale+ FPGA show that phase-shifting resolution can be adjusted down to 88 f s in these devices. To verify the performance of this method, we have deployed it in a delay characterization circuit to measure the FPGA's resources delays. The experiments show that we can measure path delays below 1 ns which is impossible in conventional frequency sweep-based methods and we reach a much finer time resolution.