Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)最新文献_第5页

Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips 基于液滴轨迹的阵列划分和引脚分配算法用于数字微流控生物芯片的自动化设计

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176283

Tao Xu, K. Chakrabarty

{"title":"Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips","authors":"Tao Xu, K. Chakrabarty","doi":"10.1145/1176254.1176283","DOIUrl":"https://doi.org/10.1145/1176254.1176283","url":null,"abstract":"Microfluidics-based biochips combine electronics with biology to open new application areas such as point-of-care medical diagnostics, on-chip DNA analysis, and automated drug discovery. Bioassays are mapped to microfluidic arrays using synthesis tools, and they are executed through the manipulation of sample and reagent droplets by electrical means. Most prior work on CAD for biochips has assumed independent control of electrodes using a large number of (electrical) input pins. Such solutions are not feasible for low-cost disposable biochips that are envisaged for many field applications. A more promising design strategy is to divide the microfluidic array into smaller partitions and use a small number of electrodes to control the electrodes in each partition. We propose a partitioning algorithm based on the concept of \"droplet trace\", which is extracted from the scheduling and droplet routing results produced by a synthesis tool. An efficient pin assignment method, referred to as the \"Connect-5 algorithm\", is combined with the array partitioning technique based on droplet traces. The array partitioning and pin assignment methods are evaluated using a set of multiplexed bioassays.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117171008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 83

Challenges in exploitation of loop parallelism in embedded applications 在嵌入式应用中利用循环并行性的挑战

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176298

A. Kejariwal, A. Veidenbaum, A. Nicolau, M. Girkar, Xinmin Tian, Hideki Saito

{"title":"Challenges in exploitation of loop parallelism in embedded applications","authors":"A. Kejariwal, A. Veidenbaum, A. Nicolau, M. Girkar, Xinmin Tian, Hideki Saito","doi":"10.1145/1176254.1176298","DOIUrl":"https://doi.org/10.1145/1176254.1176298","url":null,"abstract":"Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. How this hardware parallelism can be exploited by applications is directly related to the amount of parallelism inherent in a target application. In this paper we evaluate the performance potential of different types of parallelism, viz., true thread-level parallelism, speculative thread- level parallelism and vector parallelism, when executing loops. Applications from the industry-standard EEMBC 1.1, EEMBC 2.0 and the MiBench embedded benchmark suites are analyzed using the Intel C compiler. The results show what can be achieved today, provide upper bounds on the performance potential of different types of thread parallelism, and point out a number of issues that need to be addressed to improve performance. The latter include parallelization of libraries such as libc and design of parallel algorithms to allow maximal exploitation of parallelism. The results also point to the need for developing new benchmark suites more suitable to parallel compilation and execution.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129813716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Promises and challenges of mobile embedded system:: an industry perspective 移动嵌入式系统的前景与挑战:一个行业视角

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176257

N. Woo

引用次数: 2

Automatic generation of transaction level models for rapid design space exploration 自动生成事务级模型，用于快速设计空间探索

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176272

Dongwan Shin, A. Gerstlauer, J. Peng, R. Dömer, D. Gajski

引用次数: 28

Fuzzy decision making in embedded system design 嵌入式系统设计中的模糊决策

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176309

A. D. Nuovo, M. Palesi, Davide Patti, G. Ascia, V. Catania

{"title":"Fuzzy decision making in embedded system design","authors":"A. D. Nuovo, M. Palesi, Davide Patti, G. Ascia, V. Catania","doi":"10.1145/1176254.1176309","DOIUrl":"https://doi.org/10.1145/1176254.1176309","url":null,"abstract":"The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi- objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto- optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128118939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

A formal approach to robustness maximization of complex heterogeneous embedded systems 复杂异构嵌入式系统鲁棒性最大化的形式化方法

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176267

A. Hamann, R. Racu, R. Ernst

引用次数: 30

Key technologies for the next generation wireless communications 下一代无线通信的关键技术

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176319

Kyung-Ho Kim

引用次数: 17

Multi-processor system design with ESPAM ESPAM多处理器系统设计

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176306

Hristo Nikolov, T. Stefanov, E. Deprettere

{"title":"Multi-processor system design with ESPAM","authors":"Hristo Nikolov, T. Stefanov, E. Deprettere","doi":"10.1145/1176254.1176306","DOIUrl":"https://doi.org/10.1145/1176254.1176306","url":null,"abstract":"For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level (RTL) descriptions, mostly created by hand. Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time consuming. As an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called ESPAM for automated multiprocessor system design and implementation. ESPAM moves the design specification from RTL to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and ESPAM tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130605546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 90

Accurate yet fast modeling of real-time communication 准确而快速的实时通信建模

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176273

G. Schirner, R. Dömer

{"title":"Accurate yet fast modeling of real-time communication","authors":"G. Schirner, R. Dömer","doi":"10.1145/1176254.1176273","DOIUrl":"https://doi.org/10.1145/1176254.1176273","url":null,"abstract":"Accurate modeling of communication is a necessary part of system level design for real-time safety-critical applications. For efficient prediction of a system's performance, transaction level modeling (TLM) is often used which increases the simulation speed by orders of magnitude. The speed advantage, however, comes at the cost of low accuracy. In this paper, we use a novel modeling technique, called result oriented modeling (ROM), which yields 100% accuracy in timing, yet approaches the same speed as traditional TLM. ROM also abstracts away internal details of the communication but, in contrast to TLM, fully maintains accurate timing. ROM optimistically predicts the timing and retroactively takes corrective measures, if necessary. In this paper, we compare the ROM technique to TLM at different levels of abstraction, using a controller area network (CAN) bus example. Our results show that ROM yields a simulation speedup close to the traditional TLM, yet exhibits the same timing accuracy as a bus functional model. Thus, for safety-critical real-time applications, ROM is a viable replacement for the inaccurate TLM.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134070962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation 一种加速可重目标可移植动态编译指令集仿真的多处理方法

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176302

W. Qin, Joseph D'Errico, Xinping Zhu

{"title":"A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation","authors":"W. Qin, Joseph D'Errico, Xinping Zhu","doi":"10.1145/1176254.1176302","DOIUrl":"https://doi.org/10.1145/1176254.1176302","url":null,"abstract":"Traditionally, instruction-set simulators (ISS's) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS's have been mainly driven by the continuously improving performance of single processors. However, since the focus of processor manufacturers is shifting from frequency scaling to multiprocessing, ISS developers need to seize this opportunity for further performance growth. This paper proposes a multiprocessing approach to accelerate one class of dynamic- compiled ISS's. At the heart of the approach is a simulation engine capable of mixed interpretative and compiled simulation. The engine selects frequently executed target code blocks and translates them into dynamically loaded libraries (DLLs), which are then linked to the engine at run time. While the engine performs simulation on one processor, the translation tasks are distributed among several assistant processors. Our experiment results using SPEC CINT2000 benchmarks show that this approach achieves on average 197 million instructions per second (MIPS) for the MIPS32 IS A and 133 MIPS for the ARM V4 ISA. Compared with the uniprocessing configuration under the same general approach, multiprocessing offers higher performance and improved speed consistency. To our best knowledge, this is the first reported approach that uses multiprocessing to accelerate functional simulation.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124050878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47