Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)最新文献

Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications 数据重用驱动的能量感知的MPSoC内存和通信架构的协同合成流应用

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176326

I. Issenin, N. Dutt

{"title":"Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications","authors":"I. Issenin, N. Dutt","doi":"10.1145/1176254.1176326","DOIUrl":"https://doi.org/10.1145/1176254.1176326","url":null,"abstract":"The memory subsystem of a complex multiprocessor systems- on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP- based co-synthesis technique, a mixed ILP-based traditional two- step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126741423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Automatic phase detection for stochastic on-chip traffic generation 随机片上流量生成的自动相位检测

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176277

A. Scherrer, A. Fraboulet, T. Risset

引用次数: 33

Floorplan driven leakage power aware IP-based SoC design space exploration 平面图驱动的泄漏功率感知基于ip的SoC设计空间探索

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176284

Aseem Gupta, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir

{"title":"Floorplan driven leakage power aware IP-based SoC design space exploration","authors":"Aseem Gupta, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir","doi":"10.1145/1176254.1176284","DOIUrl":"https://doi.org/10.1145/1176254.1176284","url":null,"abstract":"Multi-million gate system-on-chip (SoC) designs increasingly rely on intellectual property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoC's floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122889108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A bus architecture for crosstalk elimination in high performance processor design 高性能处理器设计中一种消除串扰的总线结构

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176314

W. Hsieh, Po-Yuan Chen, TingTing Hwang

引用次数: 6

Decision-theoretic exploration of multiProcessor platforms 多处理器平台的决策理论探索

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176305

G. Beltrame, Dario Bruschi, D. Sciuto, C. Silvano

引用次数: 18

Retargetable code optimization with SIMD instructions 可重定向代码优化与SIMD指令

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176291

M. Hohenauer, Christoph Schumacher, R. Leupers, G. Ascheid, H. Meyr, Hans van Someren

引用次数: 13

Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations 纳米技术节点架构探索的产率预测:存储组织的模型和案例研究

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176315

A. Papanikolaou, T. Grabner, M. Corbalan, P. Roussel, F. Catthoor

引用次数: 8

Cutting across layers of abstraction:: removing obstacles from the advancement of embedded systems 跨越抽象层:消除嵌入式系统发展的障碍

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176318

K. Flautner

{"title":"Cutting across layers of abstraction:: removing obstacles from the advancement of embedded systems","authors":"K. Flautner","doi":"10.1145/1176254.1176318","DOIUrl":"https://doi.org/10.1145/1176254.1176318","url":null,"abstract":"Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features. Heterogeneous multiprocessor clusters are increasingly used to deliver the required compute power for high-end applications. Heterogeneity ensures that the necessary processing power can be delivered at high levels of efficiency at reasonable implementation cost, while the use of processors endow these systems with large degrees of flexibility. One of the key challenges with these systems is system-level programming. Traditional compiler technologies are strong at programming individual cores but leave the task of parallelization to a team of experts. The first part of this talk will describe the coupling of the compiler to the system architecture on a multi-core signal-processing cluster and illustrate how compiler technology can enable the writing of portable parallel programs for it using little more than C. As claimed above, close coupling of abstraction layers can be beneficial. This can also be illustrated at the microarchitecture - circuit boundary. The second part of the talk will describe a prototype microarchitecture which is designed explicitly to deal with issues such as silicon variation and soft errors. These features in return enable system designers to focus on the typical-case performance of their implementations without having to be over-constrained by worst-case conditions.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124322636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Demand paging for OneNANDTM Flash eXecute-in-place OneNANDTM Flash就地执行的需求分页

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176310

Yongsoo Joo, Yongseok Choi, Chanik Park, S. Chung, Eui-Young Chung, N. Chang

{"title":"Demand paging for OneNANDTM Flash eXecute-in-place","authors":"Yongsoo Joo, Yongseok Choi, Chanik Park, S. Chung, Eui-Young Chung, N. Chang","doi":"10.1145/1176254.1176310","DOIUrl":"https://doi.org/10.1145/1176254.1176310","url":null,"abstract":"NAND flash memory can provide cost-effective secondary storage in mobile embedded systems, but its lack of a random access capability means that code shadowing is generally required, taking up extra RAM space. Demand paging with NAND flash memory has recently been proposed as an alternative which requires less RAM. This scheme is even more attractive for OneNAND flash, which consists of a NAND flash array with SRAM buffers, and supports eXecute-ln-Place (XIP), which allows limited random access to data on the SRAM buffers. We introduce a novel demand paging method for OneNAND flash memory with XIP feature. The proposed on-line demand paging method with XIP adopts finite size sliding window to capture the paging history and thus predict future page demands. We particularly focus on non-critical code accesses which can disturb real-time code. Experimental results show that our method outperforms conventional LRU-based demand paging by 57% in terms of execution time and by 63% in terms of energy consumption. It even beats the optimal solution obtained from MIN, which is a conventional off-line demand paging technique by 30% and 40% respectively.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126197666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Bounded arbitration algorithm for QoS-supported on-chip communication 支持qos的片上通信的有界仲裁算法

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Pub Date : 2006-10-22 DOI: 10.1145/1176254.1176275

M. A. Faruque, Gereon Weiss, J. Henkel

引用次数: 16