Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)最新文献

{"title":"Thermal-aware high-level synthesis based on network flow method","authors":"P. Lim, Ki-Seok Chung, Taewhan Kim","doi":"10.1145/1176254.1176285","DOIUrl":"https://doi.org/10.1145/1176254.1176285","url":null,"abstract":"Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1degC and 11.8degC lower peak temperature on the average, compared to that of the conventional low-power and thermal- aware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133760302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A methodology for design of application specific deadlock-free routing algorithms for NoC systems","authors":"M. Palesi, Rickard Holsmark, Shashi Kumar, V. Catania","doi":"10.1145/1176254.1176289","DOIUrl":"https://doi.org/10.1145/1176254.1176289","url":null,"abstract":"In this paper, we present a methodology to specialize the routing algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis that routing algorithms generated by our methodology have higher adaptiveness as compared to turn-model based deadlock free routing algorithms for a mesh topology NoC architecture. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. The routing algorithms generated by the proposed methodology achieve an improvement in delay close to 50% and 30% over deterministic XY routing algorithm and adaptive odd-even routing algorithm respectively.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pack instruction generation for media pUsing multi-valued decision diagram","authors":"Hiroaki Tanaka, Y. Takeuchi, K. Sakanushi, M. Imai, Yutaka Ota, Nobu Matsumoto, M. Nakagawa","doi":"10.1145/1176254.1176292","DOIUrl":"https://doi.org/10.1145/1176254.1176292","url":null,"abstract":"SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, multi-valued decision diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that our code generation technique can generate assembly code with SIMD and pack instructions performing complex repacking of 8 packed data in registers for a commercial VLIW processor with 6 pack instructions and achieved speedup ratio of up to 7.7.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic selection of application-specific instruction-set extensions","authors":"C. Galuzzi, E. Panainte, Y. Yankova, K. Bertels, S. Vassiliadis","doi":"10.1145/1176254.1176293","DOIUrl":"https://doi.org/10.1145/1176254.1176293","url":null,"abstract":"In this paper, we present a general and an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints. The instruction selection is formulated as an ILP problem and efficient solvers can be used for finding the optimal solution. An important feature of our algorithm is that it is not restricted to basic-block level nor does it impose any limitation on the number of the newly added instructions or on the number of the inputs/outputs of these instructions. The presented results show that a significant overall application speedup is achieved even for large kernels (for ADPCM decoder the speedup ranges from times1.2 to times3.7) and that our algorithm compares well with other state-of-art algorithms for automatic instruction set extensions.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129509362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Increasing the throughput of an adaptive router in network-on-chip (NoC)","authors":"Seung Eun Lee, N. Bagherzadeh","doi":"10.1145/1176254.1176276","DOIUrl":"https://doi.org/10.1145/1176254.1176276","url":null,"abstract":"In this paper, we propose a simple and efficient mechanism to increase the throughput of an adaptive router in network-on-chip (NoC). One of the most serious disadvantages of fully adaptive wormhole routers is its performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of different clocks in a head flit and body flits, because the body flits can be forwarded immediately and the FIFO usually operates faster than route decision logic in an adaptive router. The major contributions of this paper are: 1) a proposal of a simple and efficient mechanism to improve the performance of fully adaptive wormhole routers, 2) a quantitative evaluation of the proposed mechanism showing that the proposed one can support higher throughput than a conventional one, and 3) an evaluation of hardware overhead for the proposed router. In summary, the proposed clock boosting mechanism enhances the throughput of the original adaptive router by increasing the accepted load and decreasing the average latency in the region of effective bandwidth.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124808838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Architectural support for safe software execution on embedded processors","authors":"Divya Arora, A. Raghunathan, S. Ravi, N. Jha","doi":"10.1145/1176254.1176281","DOIUrl":"https://doi.org/10.1145/1176254.1176281","url":null,"abstract":"The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety; however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the instruction set of a state-of-the-art extensible processor (Xtensa from Tensilica, Inc.) to implement them. We demonstrate the application of the proposed architectural enhancements using CCured, an existing tool for type-safe retrofitting of C programs. The tool uses a type-inferencing engine that is built around strong type-safety theory and is provably safe. Simulations of memory-safe versions of popular embedded benchmarks on a cycle-accurate simulator modeling a typical embedded system configuration indicate an average performance improvement of 2.3 times, and a maximum of 4.6 times, when using the proposed architecture. These enhancements entail minimal (less than 10%) hardware overhead to the base processor. Our approach is completely automated, and applicable to any C program, making it a promising and practical approach for addressing the growing security and reliability concerns in embedded software.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130854138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The pipeline decomposition tree:: an analysis tool for multiprocessor implementation of image processing applications","authors":"D. Ko, S. Bhattacharyya","doi":"10.1145/1176254.1176269","DOIUrl":"https://doi.org/10.1145/1176254.1176269","url":null,"abstract":"Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resource-related constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To address the challenges of mapping image processing applications onto embedded multiprocessor platforms, this paper presents a novel data structure called the pipeline decomposition tree (PDT), and an associated scheduling framework, which we refer to as PDT scheduling. PDT scheduling exploits both heterogeneous data parallelism and task-level parallelism, which are important considerations for scheduling image processing applications. This paper develops the PDT representation for system synthesis, and presents methods using the PDT to derive customized pipelined architectures that are streamlined for the given implementation constraints.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"UML and model-driven development for SoC design","authors":"W. Mueller, Y. Vanderperren","doi":"10.1145/1176254.1176255","DOIUrl":"https://doi.org/10.1145/1176254.1176255","url":null,"abstract":"Summary form only given. UML (Unified Modeling LanguageTM) as an OMG standard has received wide acceptance in software engineering over the last years. As electronic systems design moved towards software engineering, there is emerging interest for UML within the hardware community and different UML diagrams and their variations found their application in requirements specification, testbenches, architectural descriptions, and behavioral modeling. In most cases, UML is just applied as a graphical capture, though UML 2.0 meanwhile comes as a computationally complete language based on a generic metamodeling mechanism. Though it introduces considerable complexity, it is one of the key strengths of UML 2.0, providing a flexible foundation for its customization towards different application domains through so-called UML profiles, which currently receives increasing tool support and gives UML great potential to complement current C++-oriented languages for ESL design. In this context, SysML and the UML for SoC extension are already available as OMG profiles for Systems Engineering and SoC application and several proprietary profiles are under development. In that context, the concepts of the Model Driven Architecture (MDA) are of emerging interest. However, since MDA was mainly introduced for CASE tool support, its full application for hardware design still needs some investigations and certainly comes with some pitfalls. For industrial applications, the availability of appropriate tool support is crucial for deployment of UML in SoC design. UML tools currently come in different variations based on different UML versions and subsets with the support of specific flows, so that the selection of the appropriate tools becomes a key decision for the successful introduction of UML. Recently, several groups have reported positive outcomes regarding the customization of UML and tool support towards SoC design. These efforts result from collaborations between industrial users, researchers, and tool vendors, and constitute steps in the right direction. Regarding model exchange between tools, the UML-related XMI (XML Metadata Interchange) format and its relationship to SPIRIT, the emerging IEEE standard, are of additional particular interest. Partial overlaps can be identified and are currently under investigations by some projects, like SPRINT.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"3 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH","authors":"Hayden Kwok-Hay So, A. Tkachenko, R. Brodersen","doi":"10.1145/1176254.1176316","DOIUrl":"https://doi.org/10.1145/1176254.1176316","url":null,"abstract":"This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. Hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. Hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122140596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automotive electronics system, software, and local area network","authors":"Y. Furukawa, S. Kawamura","doi":"10.1145/1176254.1176256","DOIUrl":"https://doi.org/10.1145/1176254.1176256","url":null,"abstract":"In this tutorial, an overview of automotive electronic systems and details of the development methodologies are presented. Automobiles were born to enhance human mobile performance. In early development stage, automotive engineers focused to strengthen automobile engine power. Afterwards, automobiles had enough function to drive faster than any animal, but they caused some social problems such as traffic accidents, environmental problems and traffic congestions. Automotive electronic technologies have been developed in order to solve these social problems. Roles of electronic technologies on automobile functional developments For the solution to safely, environment and traffic problems, various functions are necessary which could not be completed only by mechanical systems. In this section, roles of automobile electronic systems on countermeasures to the social problems are discussed. Vehicle motion control systems, power-train control systems, navigation systems, and advanced drive assist systems are introduced and automotive functions are defined. Design requirement for automotive electronic systems architecture Electronic systems composed basically of sensors, ECU's (Electronic Control Units), actuators and human interfaces. In early days, each electronic system was designed independently. Today's automobile has various functions which could be completed by multiple electric systems. Therefore, fundamental architecture of integrated electronic systems in an automobile is important to be designed in order to optimize the total function, cost and productivity. Design and development procedure of electronic systems and software In vehicle systems and software, required functions and complexity of products are increasing. In this situation, ECU suppliers are working with efficient development methodology to achieve the highest quality. Today most common development processes are still classical V shaped process, module design and C language programming. However, several new technologies such as UML design method are tried and some of them are adopted as the standard process. Automatic testing and simulation environment are also important for the development procedure. Automotive Local Area Network Recently more and more automotive equipment are controlled electronically and the number of ECU's is increasing. The number of wire harnesses is also increasing and many problems such as the increase of weight, lack of installation space and difficulty of handling are experienced. As the solution of these problems, multiplexing with automotive Local Area Network is important to secure high speed communication as well as to decrease the weight and volume of wire harnesses. We will review technologies of automotive Local Area Network from CAN and LIN, which are currently de facto standards, to FlexRay that is about to start being adopted.","PeriodicalId":370841,"journal":{"name":"Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115778103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}