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Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000最新文献

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Optimal partitioning for FPGA based regular array implementations 基于FPGA的常规阵列实现的最优分区
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873620
Steven Derrien, S. Rajopadhye, S. Sur-Kolay
{"title":"Optimal partitioning for FPGA based regular array implementations","authors":"Steven Derrien, S. Rajopadhye, S. Sur-Kolay","doi":"10.1109/PCEE.2000.873620","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873620","url":null,"abstract":"Reconfigurable Accelerators (RAs) have the potential to provide significant speed-up over many traditional software implementations. However, their effective performance is often limited by their input/output (IO) capabilities rather than by their computational power. Hence it important to take these constraints into consideration when implementing an algorithm on such an architecture. We propose an IO conscious optimal partitioning strategy for RA based regular array implementations.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122911203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Parallel program execution with process migration 带有进程迁移的并行程序执行
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873600
P. Czarnul, H. Krawczyk
{"title":"Parallel program execution with process migration","authors":"P. Czarnul, H. Krawczyk","doi":"10.1109/PCEE.2000.873600","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873600","url":null,"abstract":"A new model of process migration is considered. There are three classes of events which could initialize the reassignment procedure: new processes spawnings or terminations, significant increases of nodes' loads by users and unexpected changes of application and system configurations. Based on these parameters suitable migration rules are defined to achieve good load balancing of a computing platform. Besides, we have created a dynamic processing environment called DAMPVM which implements these rules and allows to evaluate the usability of the proposed migration procedures.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116602975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation of a real-time distributed network simulator with PC-cluster 基于pc集群的实时分布式网络模拟器的实现
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873633
J. Martí, J. A. Hollman, J. Calviño-Fraga
{"title":"Implementation of a real-time distributed network simulator with PC-cluster","authors":"J. Martí, J. A. Hollman, J. Calviño-Fraga","doi":"10.1109/PCEE.2000.873633","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873633","url":null,"abstract":"This paper describes the implementation of a real-time power system simulator based on a distributed cluster of PC desktop computers. A real-time power system simulator based on a PC-cluster can successfully cope with the size requirements of growing power systems and the computational demands of fast transient studies. The distributed version of OVNI is used as a core solver in addition to a developed I/O interface card. Models based on the standard tool for power systems transients simulations, the EMTP program, optimized for real time performance, assure accurate simulation results.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117019272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An application of genetic algorithm for three phases screened conductors optimization 遗传算法在三相屏蔽导线优化中的应用
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873632
K. Bednarek, R. Nawrowski, A. Tomczewski
{"title":"An application of genetic algorithm for three phases screened conductors optimization","authors":"K. Bednarek, R. Nawrowski, A. Tomczewski","doi":"10.1109/PCEE.2000.873632","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873632","url":null,"abstract":"The paper presents a comparison of classical and genetic methods of dimensional optimization of three-phase heavy-current lines (busways), screened with a view to minimizing the use of material of phase conductors and their screen. A mathematical model is presented for electro-dynamical calculations of the screened line, determining the distribution of current density and temperature in the conductors and their screen, as well as electrodynamical forces. Special attention is paid to the possibility of improving the performance of optimization calculation through application of the genetic method and computers provided with several, simultaneously operating processors. Results of the calculations for various optimization methods are presented and discussion of the results is enclosed.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128273626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fault tolerance for an embedded wormhole switched network 嵌入式虫洞交换网络的容错
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873606
R. Hotchkiss, B. C. O'Neill, S. Clark
{"title":"Fault tolerance for an embedded wormhole switched network","authors":"R. Hotchkiss, B. C. O'Neill, S. Clark","doi":"10.1109/PCEE.2000.873606","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873606","url":null,"abstract":"The effectiveness of parallel and distributed systems depends heavily upon the reliability and efficiency of the method used for information transfer. To satisfy these requirements, the communication medium must supply fault tolerance throughout the communication layers, but should minimise operational overheads. The work described relates to a scalable communication system for a distributed-memory parallel processing architecture, which is constructed with message routing switches. The system employs a hardware mechanism that is local to each physical connection, which provides a distributed solution for fault detection and isolation. By isolating faults and the use of adaptive routing algorithms, networks may be designed that will maintain operability in the presence of faults. An explanation of the basic switch and fault isolation mechanism is provided. The paper concludes with implementation details of the operational hardware and details of the environment, in which it has been tested.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114199723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A framework for component-based distributed applications design. The CODE: Component Oriented Distributed Environment 基于组件的分布式应用程序设计框架。代码:面向组件的分布式环境
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873592
D. Grigoras, Stefan Mihaila
{"title":"A framework for component-based distributed applications design. The CODE: Component Oriented Distributed Environment","authors":"D. Grigoras, Stefan Mihaila","doi":"10.1109/PCEE.2000.873592","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873592","url":null,"abstract":"This paper describes the design of CODE-Component Oriented Distributed Environment, which is a framework for building component-based distributed applications. This system uses the DCOM technology to provide a flexible infrastructure that supports communication among processes spread across a local area network (Intranet). A component-oriented architecture is also defined to make an easy and intuitive access to LAN-distributed processes, through a high level of abstraction. The encapsulation of these processes into software components allows developers to compose them in different ways in order to develop correct and cost-effective distributed applications. Another feature is the visual creation of distributed applications by drag & drop. We identify the requirements of a software layer that supports LAN client-server distributed completing, and we suggest a design that meets those requirements. Though our implementation uses C++, the fundamental ideas apply to any object-oriented language that supports (D)COM programming, messaging and threads.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A parallel processing technique for electrical tree growth in solid insulating materials using cellular automata 基于元胞自动机的固体绝缘材料电树生长并行处理技术
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873634
D. Piriyakumar, P. Levi, R. Jayaganthan, R. Sarathi
{"title":"A parallel processing technique for electrical tree growth in solid insulating materials using cellular automata","authors":"D. Piriyakumar, P. Levi, R. Jayaganthan, R. Sarathi","doi":"10.1109/PCEE.2000.873634","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873634","url":null,"abstract":"One of the major problems in an electrical insulation structure is its failure while operating at normal voltage stress which is due to electrical treeing. It is well-known that this electrical tree grows progressively and is damaging locally. To analyze the electrical treeing in the laboratory, not being cost effective, computer simulations are used. We have employed a known cellular automata method with new parallel processing techniques to reduce the computation time considering the available parallel processing systems. The major advantage is that the cellular automata algorithm inherently exhibits parallelism paving the way for ample exploitation. Moreover the parallelisation has helped to understand various aspects of electrical treeing also in a simple way.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133094153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A VLSI systolic array architecture for computation of third-order cumulants for two-dimensional signals 一种用于二维信号三阶累积量计算的VLSI收缩阵列结构
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873616
Ziad H. Mussallam, R. E. Ahmed, S. Alshebeili
{"title":"A VLSI systolic array architecture for computation of third-order cumulants for two-dimensional signals","authors":"Ziad H. Mussallam, R. E. Ahmed, S. Alshebeili","doi":"10.1109/PCEE.2000.873616","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873616","url":null,"abstract":"Cumulants or higher-order statistics have been established as powerful analytical tools in modern signal processing. To estimate cumulants directly from the incoming time-series data in real-time, it is necessary to design a parallel architecture that speeds up the estimation process. This paper describes an efficient VLSI systolic array architecture for computing third-order cumulants for two-dimensional signals. The cumulants estimation algorithm is first reformulated so that any redundancy due to symmetry properties is eliminated. The architecture exploits parallelism, pipelining, and regular cell structures. The architecture, designed with 1.0 /spl mu/ CMOS process, is capable of operating at a speed of 13 MHz. Performance results, in terms of speedup and efficiency, are presented.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124381580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Introduction of the speaking rate in the model of speech recognition 语音识别模型中语速的介绍
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873603
A. Yousfi, A. Meziane
{"title":"Introduction of the speaking rate in the model of speech recognition","authors":"A. Yousfi, A. Meziane","doi":"10.1109/PCEE.2000.873603","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873603","url":null,"abstract":"We propose an improvement to the centisecond TLHMM model applied to the sound duration. Indeed, the distribution of the sound duration depends on the speaking rate. An adaptation in a post-processing step is needed. This adaptation is studied by proposing a model of the speaking rate based on average syllabic duration. The experiments elaborated on a set of BDSONS show the interest of this approach. This work is a continuation of those of (Meziane et al., 1999) and (Suaudeau, 1994).","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128613563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel Jacobi-Davidson method for multichannel blind equalization criterium 多通道盲均衡准则的平行Jacobi-Davidson方法
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873604
L. Yang
{"title":"Parallel Jacobi-Davidson method for multichannel blind equalization criterium","authors":"L. Yang","doi":"10.1109/PCEE.2000.873604","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873604","url":null,"abstract":"Some recent works have represented novel techniques that exploit cyclostationarity for channel identification in data communication systems using only second order statistics. In particular, work has shown the feasibility of blind identification based on the forward shift structure of the correlation matrices of the source. We propose an alternative high performance algorithm based on the above property but with an improved choice of the autocorrelation of the equalization matrices to be considered. The new representation of the equalization problem provides a cost function formulated as a large generalized eigenvalue problem, which can be efficiently solved by the Jacobi-Davidson method. We mainly focus on the parallel aspects of the Jacobi-Davidson method on massively distributed memory computers. The performance of this method on this kind of architecture is always limited because of the global communication required for the inner products due to the Modified Gram-Schmidt (MGS) process. We use Given rotations which require only local communications avoiding the global communication of inner products since this represents the bottleneck of the parallel performance on distributed memory computers. The corresponding data distribution and communication scheme is presented as well. Several simulation experiments over different data transmission constellations carried out on Parsytec systems are presented as well.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130437347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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