Optimal partitioning for FPGA based regular array implementations

Abstract

Reconfigurable Accelerators (RAs) have the potential to provide significant speed-up over many traditional software implementations. However, their effective performance is often limited by their input/output (IO) capabilities rather than by their computational power. Hence it important to take these constraints into consideration when implementing an algorithm on such an architecture. We propose an IO conscious optimal partitioning strategy for RA based regular array implementations.