基于FPGA的常规阵列实现的最优分区

Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI:10.1109/PCEE.2000.873620

Steven Derrien, S. Rajopadhye, S. Sur-Kolay

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引用次数: 8

摘要

与许多传统软件实现相比，可重构加速器(RAs)具有提供显著加速的潜力。然而，它们的有效性能通常受限于它们的输入/输出(IO)能力，而不是它们的计算能力。因此，在这样的体系结构上实现算法时，考虑这些约束是很重要的。我们提出了一种基于RA的正则数组实现的IO感知最优分区策略。

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Optimal partitioning for FPGA based regular array implementations

Reconfigurable Accelerators (RAs) have the potential to provide significant speed-up over many traditional software implementations. However, their effective performance is often limited by their input/output (IO) capabilities rather than by their computational power. Hence it important to take these constraints into consideration when implementing an algorithm on such an architecture. We propose an IO conscious optimal partitioning strategy for RA based regular array implementations.

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Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000

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