Czas Kultury最新文献_第10页

A SC rectification and bin-integration circuit for nerve signal processing: experimental results 一种用于神经信号处理的SC整流双积分电路:实验结果

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1302027

A. Harb, M. Sawan

{"title":"A SC rectification and bin-integration circuit for nerve signal processing: experimental results","authors":"A. Harb, M. Sawan","doi":"10.1109/ICECS.2003.1302027","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302027","url":null,"abstract":"In this paper, we describe a low-voltage CMOS switched-capacitor rectification and bin-integration (RBI) circuit dedicated to sensor electronic interfaces. The applications of these interfaces are among others, biomedical and more particularly the implantable devices. RBI is the most common signal processing function applied to the nerve signals. Since the frequency of these signals is below 10 kHz, a switched-capacitor architecture has been used. The circuit comprises an always-valid sample and hold circuit followed by a full wave rectifier. The bin-integration is then performed with three resettable integration stages. The third stage is reset in such a way to use the maximum range of the ADC. The resulting RBI signal is then converted to digital and transferred to the implant central processor where information about bladder could be extracted. The circuit has been realized in CMOS 0.35 /spl mu/m, 3.3 V technology. The design, simulation and measurement results of the proposed interface are presented. At 1.3 V supply, the measured circuit obtains an RBI error of less than -45 dB for a sinewave input of 7.2 kHz that is the main component of the nerve signal and a dynamic range of /spl plusmn/1.1 V while dissipating 578 /spl mu/W and occupying a chip area of 5.83 mm/sup 2/.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"2 1","pages":"264-267 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81080925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Colour image watermarking in the complex wavelet domain 复小波域彩色图像水印

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1301727

A. Bouridane, F. Kurugollu, Russell Beggs, S. Boussakta

引用次数: 4

Stability and performance preserving controller order reduction via Youla parameterization and LMIS 通过Youla参数化和LMIS实现控制器降阶的稳定性和性能保持

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1301872

R. Amirifar, N. Sadati

引用次数: 2

Low power high speed I/O interfaces in 0.18 /spl mu/m CMOS 0.18 /spl mu/m CMOS低功耗高速I/O接口

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1301914

Yingyi Yan, T. Szymanski

引用次数: 10

A 1.5-V 14-bit CMOS DAC with a new self-calibration technique for wireless communication systems 一种1.5 v 14位CMOS DAC，具有一种新的无线通信系统自校准技术

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1301904

S. Saeedi, S. Mehrmanesh, H. A. Aslanzadeh, S. M. Atarodi

引用次数: 4

Design of a low-power Viterbi decoder for wireless communications 用于无线通信的低功耗维特比解码器的设计

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1302037

F. Ghanipour, A. Nabavi

{"title":"Design of a low-power Viterbi decoder for wireless communications","authors":"F. Ghanipour, A. Nabavi","doi":"10.1109/ICECS.2003.1302037","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302037","url":null,"abstract":"In this paper we investigate power dissipation for the Viterbi algorithm. We modified the Viterbi algorithm in a power-aware way and employed several low-power techniques to reduce its power dissipation. The first modification is re-arranging of arithmetic operations to reduce the number and complexity of computational components. Another simplification is made in the survivor memory unit by storing only one bit to identify the previous state in the survivor path, and by assigning each register to the decision vector of each clock cycle. This approach eliminates unnecessary shift operations and enables us to apply a clock-gating technique to disable all of the registers but one. The final modification stems from the property of converging all of the trace-back paths at a same state regardless of their initial state. Thus, there is no need to store a global winner path. The schemes employed in our low-power design are precomputation, clock-gating, toggle filtering, and using double edge-triggered flip-flops. The power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 88%.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"194 1","pages":"304-307 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77575234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Almost blind channel estimation using hidden training 利用隐式训练进行信道估计

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1302042

A. Orozco-Lugo, D. McLernon, M. Lara

引用次数: 0

AGC tuning of interconnected reheat thermal systems with particle swarm optimization 基于粒子群优化的互联再热系统AGC调谐

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1302055

Y. Abdel-Magid, M. Abido

引用次数: 107

Perceptually optimised sign language video coding 感知优化的手语视频编码

Czas Kultury Pub Date : 2003-12-14 DOI: 10.1109/ICECS.2003.1301862

D. Agrafiotis, C. N. Canagarajah, D. Bull