Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems最新文献

Complete state encoding based on the theory of regions 基于区域理论的完全状态编码

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494436

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev

{"title":"Complete state encoding based on the theory of regions","authors":"J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev","doi":"10.1109/ASYNC.1996.494436","DOIUrl":"https://doi.org/10.1109/ASYNC.1996.494436","url":null,"abstract":"Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which happens when a pair of different states in an SG has the same binary encoding. A standard way to approach state coding conflicts is to add new state signals into the original specification in such a way that the original behaviour remains intact. Existing methods have not yet been able to provide such theoretical foundation for event insertion, that could yield efficient practical results when applied to large models. This paper aims at presenting such a general framework, which is based on two fundamental concepts. One is a region of states in an abstract labelled SG (called a Transition System). Regions correspond to places in the associated STG. The second concept is a speed-independence preserving set, which is strongly related to the implementability of the model in logic. Regions and their intersections offer \"nice\" structural properties that make them efficient \"construction blocks\" for event insertion. The application of our theory, through the software tool \"petrify\", to state graphs of large size has proved to be successful.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120949645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Dynamic logic in four-phase micropipelines 四相微管道的动态逻辑

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494433

S. Furber, Jianwei Liu

引用次数: 75

General conditions for the decomposition of state holding elements 状态保持元素分解的一般条件

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494437

S. Burns

引用次数: 51

Optimizing average-case delay in technology mapping of burst-mode circuits 突发模式电路技术映射中平均时延优化

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494455

P. Beerel, K. Yun, W. Chou

引用次数: 32

Static scheduling of instructions on micronet-based asynchronous processors 基于微元的异步处理器上指令的静态调度

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494440

D. Arvind, Vinod E. F. Rebello

引用次数: 4

Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems 用于设计、验证和综合大规模异步系统的状态图方法

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494448

Rakefet Kol, R. Ginosar, G. Samuel

引用次数: 13

High-performance asynchronous pipeline circuits 高性能异步流水线电路

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494434

K. Yun, P. Beerel, J. Arceo

{"title":"High-performance asynchronous pipeline circuits","authors":"K. Yun, P. Beerel, J. Arceo","doi":"10.1109/ASYNC.1996.494434","DOIUrl":"https://doi.org/10.1109/ASYNC.1996.494434","url":null,"abstract":"This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The first circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a four-phase micropipeline with burst-mode control circuits. We compare our DETDFF and four-phase implementations of a FIFO buffer with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor. We implemented Day and Woods's design and both of our designs in the MOSIS 1.2 /spl mu/m CMOS process and simulated them with a 4.6 V power supply and at 100/spl deg/C. Our SPICE simulations show that our DETDFF and four-phase designs have 70% and 30% higher throughput respectively than Day and Woods's design. This higher throughput for the DETDFF design is due to latching the data on both edges of the latch control, removing the need of a reset phase and simplifying the control structures. Our four-phase design, on the other hand, has higher throughput because of the simplified control structures and the removal of the latch enable buffers from the critical path. The four-phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128275357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 81

An efficient algorithm for deriving logic functions of asynchronous circuits 一种推导异步电路逻辑函数的有效算法

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494435

T. Miyamoto, S. Kumagai

引用次数: 6

Using partial orders for trace theoretic verification of asynchronous circuits 用偏序对异步电路进行跟踪理论验证

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494447

T. Yoneda, Takashi Yoshikawa

引用次数: 34

On the correctness of the Sproull counterflow pipeline processor 论史普罗逆流流水线处理器的正确性

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1996-03-18 DOI: 10.1109/ASYNC.1996.494443

P. Lucassen, J. T. Udding

引用次数: 6