Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems

Abstract

We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM.